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user?s manual pd789860 pd78e9860a pd789861 pd78e9861a pd789860, 789861 subseries 8-bit single-chip microcontrollers ? printed in japan document no. u14826ej4v0ud00 (4th edition) date published september 2003 n cp(k) 2000, 2003
user?s manual u14826ej4v0ud 2 [memo]
user?s manual u14826ej4v0ud 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. fip and eeprom are trademarks of nec electronics corporation. windows and windows nt are either re gistered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trad emarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc.
user?s manual u14826ej4v0ud 4 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of march, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
user?s manual u14826ej4v0ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j03.4 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 succursale fran?aise filiale italiana milano, italy tel: 02-66 75 41 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 tyskland filial taeby, sweden tel: 08-63 80 820 united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
user?s manual u14826ej4v0ud 6 major revisions in this edition pages description pp. 23, 30 chapter 1 general ( pd789860 subseries) chapter 2 general ( pd789861 subseries) ? update of 1.5 78k/0s series lineup and 2.5 78k/0s series lineup to latest version p. 37 chapter 3 pin functions ? modification of description of 3.2.9 v pp ( pd78e9860a, 78e9861a only) p. 92 chapter 9 8-bit timers 30 and 40 ? addition of description of timer input of p21 to 9.3 (4) port mode register 2 (pm2) pp. 125, 130, 131 chapter 11 power-on-clear circuits ? modification of figure 11-1 block diagram of power-on-clear circuit and figure 11-2 block diagram of low-voltage detection circuit ? addition of caution to 11.4.2 operation of low-voltage detection (lvi) circuit ? modification of figure 11-9 lvi circuit operation timing p. 133 chapter 12 bit sequential buffer ? addition of 12.3 (2) port mode register 2 (pm2) p. 159 chapter 17 pd78e9860a, 78e9861a ? addition of description of power supply volt age and osts oscillation stabilization time to table 17-1 differences between pd78e9860a, 78e9861a and mask rom versions p. 180 addition of chapter 20 electrical specifications p. 195 addition of chapter 21 example of rc oscilla tion frequency characteristics (reference values) p. 196 addition of chapter 22 package drawing p. 197 addition of chapter 23 recommended soldering conditions p. 205 addition of appendix b notes on target system design the mark shows major revised points.
user?s manual u14826ej4v0ud 7 introduction target readers this manual is intended for user engineer s who wish to understand the functions of the pd789860, 789861 subseries in order to design and develop its application systems and programs. the target devices are t he following subseries products. ? pd789860 subseries: pd789860, 78e9860a ? pd789861 subseries: pd789861, 78e9861a the system clock oscillation frequency of the ceramic/crystal oscillation ( pd789860 subseries) is described as f x and the system clock oscillation frequency of the rc oscillation ( pd789861 subseries) is described as f cc . purpose this manual is intended to give users on understanding of the f unctions described in the organization below. organization two manuals are available for the pd789860, 789861 subseries: this manual and the instruction manual (comm on to the 78k/0s series). pd789860, 789861 subseries user?s manual 78k/0s series instructions user?s manual ? pin functions ? internal block functions ? interrupts ? other internal peripheral functions ? electrical specifications ? cpu function ? instruction set ? instruction description how to use this manual it is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. to understand the overa ll functions of the pd789860, 789861 subseries read this manual in the order of the contents . how to read register formats the name of a bit whose number is enclosed with <> is reserved in the assembler and is defined in the c compiler by the header file sfrbit.h. to learn the detailed functions of a register whose register name is known see appendix c register index . to learn the details of the instru ction functions of the 78k/0s series refer to 78k/0s series instructions user?s manual (u11047e) separately available. to learn the electrical specifications of the pd789860, 789861 subseries see chapter 20 electrical specifications .
user?s manual u14826ej4v0ud 8 conventions data significance: higher digits on the left and lower digits on the right active low representation: (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd789860, 789861 subseries user?s manual this manual 78k/0s series instructions user?s manual u11047e documents related to developmen t software tools (user?s manuals) document name document no. operation u14876e language u14877e ra78k0s assembler package structured assembly language u11623e operation u14871e cc78k0s c compiler language u14872e operation (windows tm based) u15373e sm78k series system simulator ver. 2.30 or later external part user open in terface specification u15802e id78k series integrated debugger ver. 2.30 or later operation (windows based) u15185e project manager ver. 3.12 or later (windows based) u14610e documents related to development hardware tools (user?s manuals) document name document no. ie-78k0s-ns in-circuit emulator u13549e ie-78k0s-ns-a in-circuit emulator u15207e ie-789860-ns-em1 emulation board u16499e caution the related docum ents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
user?s manual u14826ej4v0ud 9 documents related to eeprom (program memory) writing document name document no. pg-fp3 flash memory progr ammer user?s manual u13502e pg-fp4 flash memory progr ammer user?s manual u15260e other related documents document name document no. semiconductor selection guide - products and packages - x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device mount manual? webs ite (http://www.necel.com/pkg/en/mount/index.html). caution the related docum ents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
user?s manual u14826ej4v0ud 10 contents chapter 1 general ( pd789860 subseries)............................... .............................................21 1.1 features ................................................................................................................... ...................21 1.2 applications............................................................................................................... .................21 1.3 ordering information ....................................................................................................... ..........21 1.4 pin configuration (top view )............................................................................................... .....22 1.5 78k/0s series lineup....................................................................................................... ..........23 1.6 block diagram .............................................................................................................. ..............26 1.7 overview of functions...................................................................................................... .........27 chapter 2 general ( pd789861 subseries)............................... .............................................28 2.1 features ................................................................................................................... ...................28 2.2 applications............................................................................................................... .................28 2.3 ordering information ....................................................................................................... ..........28 2.4 pin configuration (top view )............................................................................................... .....29 2.5 78k/0s series lineup....................................................................................................... ..........30 2.6 block diagram .............................................................................................................. ..............33 2.7 overview of functions...................................................................................................... .........34 chapter 3 pin functio ns .................................................................................................... ...........35 3.1 pin function list .......................................................................................................... ..............35 3.2 description of pin functions ............................................................................................... .....36 3.2.1 p00 to p07 (por t 0)...................................................................................................... ................36 3.2.2 p20, p 21 (por t 2)........................................................................................................ .................36 3.2.3 p40 to p43 (por t 4)...................................................................................................... ................36 3.2.4 reset .................................................................................................................... ....................36 3.2.5 x1, x2 ( pd789860 subser ies)...................................................................................................36 3.2.6 cl1, cl2 ( pd789861 subser ies) ..............................................................................................36 3.2.7 v dd ............................................................................................................................... ................37 3.2.8 v ss ............................................................................................................................... ................37 3.2.9 v pp ( pd78e9860a, 78e9861a only) ..........................................................................................37 3.2.10 ic (mask ro m versi on onl y).............................................................................................. ..........37 3.3 pin i/o circuits and recommended connection of unused pins.........................................38 chapter 4 cpu architecture ................................................................................................. .....39 4.1 memory space ............................................................................................................... .............39 4.1.1 internal progr am memory space............................................................................................ ......41 4.1.2 internal dat a memory space ............................................................................................... .........41 4.1.3 special function register (s fr) area..................................................................................... .......42 4.1.4 data memo ry addre ssing................................................................................................... ..........42 4.2 processor registers ........................................................................................................ ..........44 4.2.1 control regist ers ........................................................................................................ ..................44
user?s manual u14826ej4v0ud 11 4.2.2 general-pur pose regi sters................................................................................................ ........... 46 4.2.3 special functi on register s (sfrs) ........................................................................................ ........ 47 4.3 instruction address addressing ................................... .......................................................... .49 4.3.1 relative addre ssing ...................................................................................................... ............... 49 4.3.2 immediat e addre ssing ..................................................................................................... ............ 50 4.3.3 table indi rect addr essing ................................................................................................ ............ 50 4.3.4 register addre ssing ...................................................................................................... .............. 51 4.4 operand address addressing........................................ ......................................................... .52 4.4.1 direct addressi ng ........................................................................................................ ................ 52 4.4.2 short dire ct addre ssing .................................................................................................. ............. 53 4.4.3 special function r egister (sfr ) addre ssing ............................................................................... .. 54 4.4.4 register addre ssing ...................................................................................................... .............. 55 4.4.5 register i ndirect addr essing ............................................................................................. ........... 56 4.4.6 based addressi ng......................................................................................................... ............... 57 4.4.7 stack addressi ng......................................................................................................... ................ 57 chapter 5 eeprom (data memory).............................. .............................................................. 58 5.1 memory space............................................................................................................... ............. 58 5.2 eeprom configuration....................................................................................................... ...... 58 5.3 eeprom control register .................................................................................................... .... 58 5.4 notes for eeprom writing ................................................................................................... .... 61 chapter 6 port f unctions................................................................................................... ........ 63 6.1 port functions............................................................................................................. ............... 63 6.2 port configuration ......................................................................................................... ............ 63 6.2.1 po rt 0................................................................................................................... ........................ 64 6.2.2 po rt 2................................................................................................................... ........................ 65 6.2.3 po rt 4................................................................................................................... ........................ 66 6.3 port function control registers . ........................................................................................... .. 67 6.4 operation of port functions ..................................... ........................................................... ..... 68 6.4.1 writing to i/o port ...................................................................................................... .................. 68 6.4.2 reading fr om i/o port.................................................................................................... .............. 68 6.4.3 arithmetic operation of i/o port......................................................................................... ........... 68 chapter 7 clock generator ( pd789860 subseries) ....................................................... 69 7.1 clock generator functions......................................... ......................................................... ..... 69 7.2 clock generator configuration .................................. ............................................................ .. 69 7.3 clock generator control register.............................. ............................................................. .70 7.4 system clock oscillators................................................................................................... ....... 71 7.4.1 system cl ock osc illator .................................................................................................. .............. 71 7.4.2 examples of incorre ct resonator connec tion............................................................................... .72 7.4.3 frequen cy divi der........................................................................................................ ................ 73 7.5 clock generator operation....................................... ........................................................... ..... 74 7.6 changing setting of cpu clock .............................................................................................. .75 7.6.1 time required for switching cp u clock.................................................................................... .... 75
user?s manual u14826ej4v0ud 12 7.6.2 switchi ng cpu cl ock ...................................................................................................... .............75 chapter 8 clock generator ( pd789861 subseries) .......................................................76 8.1 clock generator functions .................................................................................................. .....76 8.2 clock generator configuration .................................... .......................................................... ..76 8.3 clock generator control register................................ ........................................................... .77 8.4 system clock oscillators ................................................................................................... .......78 8.4.1 system cl ock osc illator .................................................................................................. ..............78 8.4.2 examples of incorre ct resonator connec tion............................................................................... .79 8.4.3 frequen cy divi der ........................................................................................................ ................80 8.5 clock generator operatio n .................................................................................................. .....81 8.6 changing setting of cpu clock.............................................................................................. ..82 8.6.1 time required for switching cp u clock .................................................................................... ....82 8.6.2 switchi ng cpu cl ock ...................................................................................................... .............82 chapter 9 8-bit timers 30 and 40............ ............................................................................ ......83 9.1 8-bit timers 30, 40 functions .............................................................................................. .....83 9.2 8-bit timers 30, 40 configuration............................. ............................................................. ...84 9.3 8-bit timers 30, 40 control registers .......................... ............................................................ 88 9.4 8-bit timers 30, 40 operation .............................................................................................. .....93 9.4.1 operation as 8-bit time r count er ......................................................................................... .........93 9.4.2 operation as 16-bit time r count er ........................................................................................ ......102 9.4.3 operation as carrier generat or........................................................................................... ........109 9.4.4 operation as pwm output (timer 40 onl y).................................................................................. 114 9.5 notes on using 8-bit timers 30, 40.............................. ..........................................................1 16 chapter 10 watchdog timer .................................................................................................. ...118 10.1 watchdog timer functions.................................................................................................. ...118 10.2 watchdog timer configuration .... .......................................................................................... 119 10.3 watchdog timer control register s........................................................................................12 0 10.4 watchdog timer operation .................................................................................................. ...122 10.4.1 operation as watchdog timer............................................................................................. ........122 10.4.2 operation as interval timer............................................................................................. ............123 chapter 11 power-on-clear circuits ........................... ........................................................124 11.1 power-on-clear circuit functions.................................. ........................................................ 124 11.2 power-on-clear circuit configur ation ...................................................................................124 11.3 power-on-clear circuit control registers................... ..........................................................126 11.4 power-on-clear circuit operatio n .......................................................................................... 128 11.4.1 power-on-clear (p oc) circuit operatio n .................................................................................. ...128 11.4.2 operation of low-volt age detection (lvi ) circ uit ........................................................................ .130 chapter 12 bit sequential buffer .............................. ..........................................................13 2 12.1 bit sequential buffer functions ................................... ........................................................ ..132
user?s manual u14826ej4v0ud 13 12.2 bit sequential buffer configuration......................... .............................................................. 132 12.3 bit sequential buffer control register ...................... ............................................................ 13 3 12.4 bit sequential buffer operation ............................... ............................................................ ..134 chapter 13 key return circuit................................. ............................................................ ..135 13.1 key return circuit function ..................................... .......................................................... .... 135 13.2 key return circuit configuration and operation ... .............................................................. 135 chapter 14 interrupt functions ................................... ......................................................... 1 36 14.1 interrupt function typ es.................................................................................................. ....... 136 14.2 interrupt sources and configuratio n..................................................................................... 13 7 14.3 interrupt function control register s..................................................................................... 1 39 14.4 interrupt servicing operation ............................................................................................. .... 141 14.4.1 non-maskable interrupt r equest acknowledgment operatio n..................................................... 141 14.4.2 maskable interrupt reques t acknowledgment operatio n ............................................................ 143 14.4.3 multiple inte rrupt serv icing............................................................................................ ............. 146 14.4.4 interrupt request pending ............................................................................................... ........... 147 chapter 15 standby function...................................... .......................................................... ..148 15.1 standby function and configuratio n .................................................................................... 148 15.1.1 standby functi on........................................................................................................ ................ 148 15.1.2 standby function control r egist er ....................................................................................... ........ 149 15.2 standby function operation ...................................... .......................................................... ..150 15.2.1 halt mode ............................................................................................................... ................ 150 15.2.2 stop mode ............................................................................................................... ............... 153 chapter 16 reset function .................................................................................................. ..... 156 chapter 17 pd78e9860a, 78e9861a ........................................................................................... 159 17.1 eeprom features (program memory) ......................... ......................................................... 160 17.1.1 programmi ng envir onment ................................................................................................. ....... 160 17.1.2 communi cation mode ...................................................................................................... ......... 161 17.1.3 on-board pi n proce ssing ................................................................................................. .......... 164 17.1.4 connection of adapter for eeprom wr iting .............................................................................. 16 7 chapter 18 mask options .................................................................................................... ....... 169 chapter 19 instruction set overview..................... ............................................................ 170 19.1 operation ................................................................................................................. ................. 170 19.1.1 operand identifiers and description methods ............................................................................ 1 70 19.1.2 description of ?operation? column....................................................................................... ...... 171 19.1.3 description of ?flag? column............................................................................................ .......... 171 19.2 operation list............................................................................................................ ............... 172
user?s manual u14826ej4v0ud 14 19.3 instructions listed by addr essing type ...............................................................................177 chapter 20 electrical specifications ....................... ..........................................................180 chapter 21 example of rc osci llation frequency characteristics (reference values)...............................................................................................195 chapter 22 package drawing ................................................................................................. .196 chapter 23 recommended soldering conditions... ........................................................197 appendix a development tools............................................................................................... 199 a.1 software package ........................................................................................................... .........201 a.2 language processing software ........................................ .....................................................20 1 a.3 control software ........................................................................................................... ...........202 a.4 eeprom (program memory) writing tools .................. ........................................................202 a.5 debugging tools (hardwar e) ................................................................................................. .203 a.6 debugging tools (software) ................................................................................................. ..204 appendix b notes on target system design ...................................................................205 appendix c register index .................................................................................................. .......206 c.1 register name index (in alphabetical order).......... ..............................................................206 c.2 register symbol index (in alphabetical order) ...... ..............................................................207 appendix d revision history ................................................................................................ .....208
user?s manual u14826ej4v0ud 15 list of figures (1/4) figure no. title page 3-1 pin i/o circuit s........................................................................................................... .....................................38 4-1 memory map ( pd789860, 789861) .............................................................................................................. .39 4-2 memory map ( pd78e9860a, 78e 9861a) .....................................................................................................40 4-3 data memory addressing ( pd789860, 789861) ...........................................................................................42 4-4 data memory addressing ( pd78e9860a, 78e 9861a) ..................................................................................43 4-5 program counter configur ation .............................................................................................. ........................44 4-6 program status wo rd confi guratio n .......................................................................................... .....................44 4-7 stack pointer configur ation ................................................................................................ ............................45 4-8 data to be sav ed to sta ck memory ........................................................................................... .....................45 4-9 data to be restor ed from sta ck memory ...................................................................................... .................45 4-10 general-purpose regi ster confi guratio n .................................................................................... ....................46 5-1 eeprom bl ock di agram ....................................................................................................... .........................58 5-2 format of eeprom writ e control r egister 10 ................................................................................. ..............59 6-1 block diagram of p00 to p07 ................................................................................................ ..........................64 6-2 block diagr am of p20 ....................................................................................................... ..............................65 6-3 block diagr am of p21 ....................................................................................................... ..............................66 6-4 block diagram of p40 to p43 ................................................................................................ ..........................66 6-5 format of port mode r egister............................................................................................... ..........................67 7-1 block diagram of clock g enerat or........................................................................................... .......................69 7-2 format of processor clock control regist er................................................................................. ..................70 7-3 external circuit of system clock oscilla tor................................................................................ .....................71 7-4 examples of incorre ct resonator connec tion................................................................................. ................72 7-5 switching between s ystem clock and cpu clo ck ............................................................................... ..........75 8-1 block diagram of clock g enerat or........................................................................................... .......................76 8-2 format of processor clock control regist er................................................................................. ..................77 8-3 external circuit of system clock oscilla tor................................................................................ .....................78 8-4 examples of incorre ct resonator connec tion................................................................................. ................79 8-5 switching between s ystem clock and cpu clo ck ............................................................................... ..........82 9-1 timer 30 bl ock di agram ..................................................................................................... ............................85 9-2 timer 40 bl ock di agram ..................................................................................................... ............................86 9-3 block diagram of out put controller (timer 40) .............................................................................. .................87
user?s manual u14826ej4v0ud 16 list of figures (2/4) figure no. title page 9-4 format of 8-bit timer mode control r egister 30............................................................................. ................89 9-5 format of 8-bit timer mode control r egister 40............................................................................. ................90 9-6 format of carrier generator output control register 40 ..................................................................... ...........91 9-7 format of port mode regist er 2 ............................................................................................. .........................92 9-8 timing of interval timer operation with 8-bit resolution (basic o perati on)................................................. ...95 9-9 timing of interval timer operation with 8- bit resolution (when crn0 is cleared to 00h).............................95 9-10 timing of interval timer operation with 8-bit resolution (when cr n0 is set to ffh) ...................................96 9-11 timing of interval timer operation with 8- bit resolution (when crn0 changes from n to m (n < m))..........96 9-12 timing of interval timer operation with 8- bit resolution (when crn0 changes from n to m (n > m))..........97 9-13 timing of interval timer operation with 8-bit re solution (when timer 40 match signal is selected for timer 30 c ount clo ck) .......................................................................................................... ..........................98 9-14 timing of operation of external event counter with 8-bit reso luti on ....................................................... ......99 9-15 timing of square-wave ou tput with 8-bi t resolu tion ........................................................................ ...........101 9-16 timing of interval timer o peration with 16-bi t resolu tion ................................................................. ...........104 9-17 timing of external event counter operation with 16- bit reso luti on ......................................................... ....106 9-18 timing of square-wave ou tput with 16-bi t resolu tion ....................................................................... ..........108 9-19 timing of carrier generator o peration (when cr40 = n, crh40 = m (m > n))...........................................111 9-20 timing of carrier generator o peration (when cr40 = n, crh40 = m (m < n))...........................................112 9-21 timing of carrier generator operation (when cr 40 = crh40 = n) ............................................................1 13 9-22 pwm output mode timi ng (basic o perati on) .................................................................................. .............115 9-23 pwm output mode timing (when cr40 and crh40 are ov erwritt en)........................................................ 115 9-24 case of error occurr ence of up to 1.5 clocks.............................................................................. .................116 9-25 counting operation if timer is started when tmi is high ................................................................... .........117 9-26 timing of operation as external event counter (8 -bit reso luti on) .......................................................... .....117 10-1 block diagram of watchdog timer........................................................................................... .....................119 10-2 format of timer clock selection r egister 2................................................................................ ..................120 10-3 format of watchdog timer mode regist er .................................................................................... ...............121 11-1 block diagram of power-on-clear circu it................................................................................... ...................125 11-2 block diagram of low-v oltage detect ion cir cuit ............................................................................ ...............125 11-3 format of power-on- clear regi ster 1 ....................................................................................... ....................126 11-4 format of low-voltage detection r egister 1................................................................................ .................127 11-5 format of low-voltage detecti on level selecti on regist er 1 ................................................................ .......127 11-6 timing of internal reset signal generat ion when poc circuit no rmally oper ating .....................................128 11-7 timing of internal reset signal gener ation when poc circuit normally halted ..........................................129 11-8 timing of internal reset signal generation in poc switching circu it....................................................... ....129
user?s manual u14826ej4v0ud 17 list of figures (3/4) figure no. title page 11-9 lvi circuit o peration timing .............................................................................................. ...........................131 12-1 block diagram of bit sequentia l buffer .................................................................................... .....................132 12-2 format of bit sequential buffer output control register 10 ................................................................ .........133 12-3 format of port mode regist er 2............................................................................................ ........................133 12-4 operation timing of bit sequentia l buffer................................................................................. ....................134 13-1 block diagram of key return circu it....................................................................................... ......................135 13-2 generation timing of key return interr upt ................................................................................. ..................135 14-1 basic configuration of interrupt func tion................................................................................. .....................138 14-2 format of interrupt request flag r egister 0............................................................................... ..................139 14-3 format of interrupt mask flag regi ster 0 .................................................................................. ...................140 14-4 program status wo rd confi guratio n ......................................................................................... ....................140 14-5 flowchart from non-maskable interrupt r equest generation to ack nowledgment (i ntwdt)......................142 14-6 timing of non-maskable in terrupt request acknowl edgment ................................................................... ...142 14-7 acknowledgment of non -maskable interr upt r equest .......................................................................... ........142 14-8 interrupt request acknowl edgment processi ng algor ithm ..................................................................... ......144 14-9 interrupt request acknowledgment timing (example of mov a, r) ............................................................. 144 14-10 interrupt request acknowledgment timing (when inte rrupt request flag is set at last clock during instruction execut ion) ......................................................................................................... ..........................145 14-11 example of mult iple inte rrupts........................................................................................... ............................146 15-1 format of oscillation stabilizat ion time select ion regi ster ............................................................... ...........149 15-2 releasing halt mode by in terrupt.......................................................................................... .....................151 15-3 releasing halt mode by r eset i nput ........................................................................................ ...............152 15-4 releasing stop mode by in terrupt .......................................................................................... ....................154 15-5 releasing stop mode by r eset i nput........................................................................................ ...............155 16-1 block diagram of reset f uncti on........................................................................................... .......................156 16-2 reset timing by reset input ............................................................................................... .......................157 16-3 reset timing by wa tchdog timer overflow................................................................................... ...............157 16-4 reset timing by reset input in stop mode.................................................................................. ............157 17-1 environment for writing program to eeprom (progr am memo ry) ..............................................................16 0 17-2 communication mode selection format ....................................................................................... ................161 17-3 example of connection with dedicated flas h progra mmer ..................................................................... .....162
user?s manual u14826ej4v0ud 18 list of figures (4/4) figure no. title page 17-4 v pp pin connecti on exam ple ........................................................................................................ ................164 17-5 signal conflict (input pi n of serial interf ace)........................................................................... ......................165 17-6 abnormal operati on of other device ........................................................................................ ....................165 17-7 signal conflic t (reset pin)............................................................................................... ...........................166 17-8 wiring example for eeprom wr iting adapter wit h pseudo 3- wire.............................................................. 167 a-1 developm ent t ools .......................................................................................................... .............................200 b-1 connection condi tion of target............................................................................................. ........................205
user?s manual u14826ej4v0ud 19 list of tables (1/2) table no. title page 3-1 types of pin i/o circuits and re commended connection of unused pins .....................................................38 4-1 internal rom capac ity...................................................................................................... ..............................41 4-2 vector table ............................................................................................................... ....................................41 4-3 special func tion regi sters ................................................................................................. ............................48 5-1 eeprom write time (when operating at f x = 5.0 mhz)................................................................................60 5-2 eeprom write time (when operating at f cc = 1.0 mhz)..............................................................................60 6-1 port functi ons............................................................................................................. ....................................63 6-2 configurat ion of port ...................................................................................................... .................................63 6-3 port mode register and output latch settings for using al ternate f unctions ................................................6 7 7-1 configuration of clock g enerat or........................................................................................... .........................69 7-2 maximum time required for switchi ng cpu clock .............................................................................. ..........75 8-1 configuration of clock g enerat or........................................................................................... .........................76 8-2 maximum time required for switchi ng cpu clock .............................................................................. ..........82 9-1 mode list .................................................................................................................. ......................................83 9-2 configuration of 8-bit timers 30, 40 ....................................................................................... ........................84 9-3 interval time of timer 30 (during f x = 5.0 mhz o perati on).............................................................................94 9-4 interval time of timer 30 (during f cc = 1.0 mhz o perati on)........................................................................... 94 9-5 interval time of timer 40 (during f x = 5.0 mhz o perati on).............................................................................94 9-6 interval time of timer 40 (during f cc = 1.0 mhz o perati on)........................................................................... 94 9-7 square-wave output range of timer 40 (during f x = 5.0 mhz o perati on) .................................................. 100 9-8 square-wave output range of timer 40 (during f cc = 1.0 mhz o perati on) ................................................ 100 9-9 interval time with 16-bit resolution (during f x = 5.0 mhz o perati on) .......................................................... 103 9-10 interval time with 16-bit resolution (during f cc = 1.0 mhz o perati on) ........................................................ 103 9-11 square-wave output range with 16-bit resolution (during f x = 5.0 mhz o perati on).................................. 107 9-12 square-wave output range with 16-bit resolution (during f cc = 1.0 mhz o perati on) ................................ 107 10-1 inadvertent program loop dete ction time of watchdog ti mer ................................................................. ...118 10-2 interval time of watchdog timer ........................................................................................... .......................118 10-3 configuration of watchdog timer ........................................................................................... ......................119 10-4 inadvertent program loop dete ction time of watchdog ti mer ................................................................. ...122 10-5 interval time of watchdog timer ........................................................................................... .......................123
user?s manual u14826ej4v0ud 20 list of tables (2/2) table no. title page 12-1 configuration of bit sequentia l buffer .................................................................................... .......................132 14-1 interrupt sour ces......................................................................................................... ..................................137 14-2 interrupt request si gnals and corres ponding fl ags......................................................................... ............139 14-3 time from generation of maskabl e interrupt request to serv icing........................................................... ....143 15-1 operation status es in ha lt mode........................................................................................... .....................150 15-2 operation after re leasing ha lt mode ....................................................................................... ..................152 15-3 operation status es in st op mode ........................................................................................... ....................153 15-4 operation after re leasing st op mode ....................................................................................... .................155 16-1 status of hard ware afte r reset............................................................................................ .........................158 17-1 differences between pd78e9860a, 78e9861a and ma sk rom vers ions .................................................159 17-2 communicati on mode list................................................................................................... ..........................161 17-3 pin connec tion li st ....................................................................................................... ................................163 19-1 operand identifiers and descripti on met hods ............................................................................... ................170 23-1 surface mounting ty pe soldering conditi ons ................................................................................ ...............197
user?s manual u14826ej4v0ud 21 chapter 1 general ( pd789860 subseries) 1.1 features rom and ram capacity data memory item product name program memory (rom) internal high-speed ram eeprom tm pd789860 mask rom 4 kb pd78e9860a eeprom 4 kb 128 bytes 32 bytes system clock: ceramic/crystal oscillation minimum instruction execution ti me can be changed from high-speed (0.4 s) to low-speed (1.6 s) at 5.0 mhz operation with system clock. i/o ports: 14 timer: 3 channels 8-bit timer: 2 channels watchdog timer: 1 channel on-chip power-on-clear circuit on-chip bit sequential buffer power supply voltage: v dd = 1.8 to 5.5 v operating ambient temperature: t a = ? 40 to +85 c 1.2 applications keyless entry and other autom otive electrical equipment. 1.3 ordering information part number package internal rom pd789860mc- -5a4 20-pin plastic ssop (7.62 mm (300)) mask rom pd78e9860amc-5a4 20-pin plastic ssop (7.62 mm (300)) eeprom remark indicates rom code suffix.
chapter 1 general ( pd789860 subseries) user?s manual u14826ej4v0ud 22 1.4 pin configuration (top view) 20-pin plastic ssop (7.62 mm (300)) pd789860mc- -5a4 pd78e9860amc-5a4 reset x1 x2 v ss ic (v pp ) v dd p00 p01 p02 p03 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 p21/tmi p20/tmo/bsfo p07 p06 p05 p04 p43/kr13 p42/kr12 p41/kr11 p40/kr10 caution connect the ic (internally connected) pin directly to v ss . remark pin connections in parenthes es are intended for the pd78e9860a. bsfo: bit sequential buffer output tmi: timer input ic: internally connected tmo: timer output kr10 to kr13: key return v dd : power supply p00 to p07: port 0 v pp : programming power supply p20, p21: port 2 v ss : ground p40 to p43: port 4 x1, x2: crystal/ceramic oscillator reset: reset
chapter 1 general ( pd789860 subseries) user?s manual u14826ej4v0ud 23 1.5 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. 80-pin sio, 8-bit a/d converter, and resistance division type lcd (28 4) 52-pin 52-pin sio and resistance division type lcd (24 4) 8-bit a/d and on-chip voltage booster type lcd (23 4) pd789327 pd789467 pd789446 pd789436 pd789426 pd789306 pd789316 pd789426 with enhanced a/d converter (10 bits) pd789446 with enhanced a/d converter (10 bits) sio, 8-bit a/d, and on-chip voltage booster type lcd (15 4) sio, 8-bit a/d, and on-chip voltage booster type lcd (5 4) rc oscillation version of the pd789306 sio and on-chip voltage booster type lcd (24 4) 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin pd789407a pd789456 lcd drive 80-pin pd789417a pd789407a with enhanced a/d converter (10 bits) sio, 10-bit a/d converter, and on-chip voltage booster type lcd (28 4) 80-pin sio, 8-bit a/d converter, and resistance division type lcd (28 4) 80-pin pd789478 pd789488 pd789881 64-pin uart and resistance division type lcd (26 4) products under development products in mass production pd789014 small-scale package, general-purpose applications 78k/0s series 28-pin pd789014 with enhanced timer and increased rom, ram capacity on-chip uart and capable of low voltage (1.8 v) operation pd789074 with added subsystem clock pd789146 pd789156 44-pin small-scale package, general-purpose applications and a/d converter 44-pin 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789177 pd789167 30-pin 30-pin pd789104a pd789114a pd789167 with enhanced a/d converter (10 bits) pd789104a with enhanced timer pd789124a with enhanced a/d converter (10 bits) rc oscillation version of the pd789104a pd789104a with enhanced a/d converter (10 bits) pd789026 with added 8-bit a/d converter and multiplier pd789104a with added eeprom pd789146 with enhanced a/d converter (10 bits) pd789177y pd789167y y subseries products support smb. 88-pin pd789830 pd789835 144-pin uart and dot lcd (40 16) uart, 8-bit a/d, and dot lcd (total display output pins: 96) 42-/44-pin 44-pin pd789074 30-pin pd789026 with enhanced timer 30-pin pd789074 with enhanced timer and increased rom, ram capacity pd789088 pd789046 pd789026 usb 44-pin pd789800 for pc keyboard and on-chip usb function inverter control 44-pin pd789842 on-chip inverter controller and uart vfd drive 52-pin pd789871 on-chip vfd controller (total display output pins: 25) keyless entry 20-pin pd789860 pd789861 20-pin on-chip poc and key return circuit rc oscillation version of the pd789860 on-chip bus controller pd789850a on-chip can controller meter control pd789052 20-pin pd789860 without eeprom, poc, and lvi pd789062 20-pin rc oscillation version of the pd789052 pd789862 30-pin 30-pin 44-pin pd789860 with enhanced timer, added sio, and increased rom, ram capacity pd789852 pd789850a with enhanced functions such as timer and a/d converter remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same.
chapter 1 general ( pd789860 subseries) user?s manual u14826ej4v0ud 24 the major functional differences bet ween the subseries are listed below. series for general-purpose applications and lcd drive timer v dd function subseries name rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remarks pd789046 16 kb 1 ch pd789026 4 kb to 16 kb 1 ch 34 pd789088 16 kb to 32 kb 3 ch pd789074 2 kb to 8 kb 1 ch 1 ch 24 pd789014 2 kb to 4 kb 1 ch (uart: 1 ch) 22 ? pd789062 rc oscillation version small-scale package, general- purpose applications pd789052 4 kb 2 ch ? ? 1 ch ? ? ? 14 1.8 v ? pd789177 ? 8 ch pd789167 16 kb to 24 kb 3 ch 1 ch 8 ch ? 31 ? pd789156 ? 4 ch pd789146 8 kb to 16 kb 4 ch ? on-chip eeprom pd789134a ? 4 ch pd789124a 4 ch ? rc oscillation version pd789114a ? 4 ch small-scale package, general- purpose applications and a/d converter pd789104a 2 kb to 8 kb 1 ch 1 ch ? 1 ch 4 ch ? 1 ch (uart: 1 ch) 20 1.8 v ? pd789835 24 kb to 60 kb 6 ch ? 3 ch 37 1.8 v note pd789830 24 kb 1 ch ? 1 ch (uart: 1 ch) 30 2.7 v dot lcd supported pd789488 32 kb to 48 kb ? 8 ch pd789478 24 kb to 48 kb 8 ch ? 2 ch (uart: 1 ch) 45 pd789417a ? 7 ch pd789407a 12 kb to 24 kb 3 ch 7 ch ? 43 pd789456 ? 6 ch pd789446 6 ch ? 30 pd789436 ? 6 ch pd789426 12 kb to 16 kb 6 ch 1 ch (uart: 1 ch) 40 ? pd789316 rc oscillation version pd789306 8 kb to 16 kb 1 ch ? 2 ch (uart: 1 ch) 23 pd789467 1 ch ? 18 lcd drive pd789327 4 kb to 24 kb 2 ch ? 1 ch 1 ch ? ? 1 ch 21 1.8 v ? note flash memory version: 3.0 v
chapter 1 general ( pd789860 subseries) user?s manual u14826ej4v0ud 25 series for assp timer v dd function subseries name rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remarks usb pd789800 8 kb 2 ch ? ? 1 ch ? ? 2 ch (usb: 1 ch) 31 4.0 v ? inverter control pd789842 8 kb to 16 kb 3 ch note 1 1 ch 1 ch 8 ch ? 1 ch (uart: 1 ch) 30 4.0 v ? pd789852 24 kb to 32 kb 3 ch ? 8 ch 3 ch (uart: 2 ch) 31 on-chip bus controller pd789850a 16 kb 1 ch 1 ch ? 1 ch 4 ch ? 2 ch (uart: 1 ch) 18 4.0 v ? pd789861 rc oscillation version, on- chip eeprom pd789860 4 kb 2 ch ? ? 14 keyless entry pd789862 16 kb 1 ch 2 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 22 1.8 v on-chip eeprom vfd drive pd789871 4 kb to 8 kb 3 ch ? 1 ch 1 ch ? ? 1 ch 33 2.7 v ? meter control pd789881 16 kb 2 ch 1 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 28 2.7 v note 2 ? notes 1. 10-bit timer: 1 channel 2. flash memory version: 3.0 v
chapter 1 general ( pd789860 subseries) user?s manual u14826ej4v0ud 26 1.6 block diagram port 0 p00 to p07 port 2 p20, p21 v dd v ss ic (v pp ) tmi/p21 watchdog timer system control reset x1 x2 port 4 p40 to p43 78k/0s cpu core rom 8-bit timer/ event counter 40 8-bit timer 30 cascaded 16-bit timer counter tmo/p20 bit seq. buffer ram eeprom key return 10 kr10/p40 to kr13/p43 power on clear power on clear low voltage indicator bsfo/p20 remark pin connections in parenthes es are intended for the pd78e9860a.
chapter 1 general ( pd789860 subseries) user?s manual u14826ej4v0ud 27 1.7 overview of functions part number item pd789860 pd78e9860a mask rom eeprom rom 4 kb high-speed ram 128 bytes internal memory eeprom 32 bytes oscillator ceramic/crystal oscillator minimum instruction execution time 0.4/1.6 s (@5.0 mhz operation with system clock) general-purpose registers 8 bits 8 registers instruction set 16-bit operations bit manipulations (such as set, reset, and test) i/o ports total: 14 cmos i/o: 10 cmos input: 4 timers 8-bit timer: 2 channels watchdog timer: 1 channel poc circuit generates internal reset signal according to co mparison of detection voltage to power supply voltage power-on-clear circuit lvi circuit generates interrupt request signal according to comparison of detection voltage to power supply voltage bit sequential buffer 8 bits 8 bits = 16 bits key return function generates key return signal according to falling edge detection maskable internal: 5 vectored interrupt sources non-maskable internal: 1, external: 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to + 85c package 20-pin plastic ssop (7.62 mm (300))
user?s manual u14826ej4v0ud 28 chapter 2 general ( pd789861 subseries) 2.1 features rom and ram capacity data memory item product name program memory (rom) internal high-speed ram eeprom pd789861 mask rom 4 kb pd78e9861a eeprom 4 kb 128 bytes 32 bytes system clock: rc oscillation minimum instruction execution ti me can be changed from high-speed (2.0 s) to low-speed (8.0 s) at 1.0 mhz operation with system clock. i/o ports: 14 timer: 3 channels 8-bit timer: 2 channels watchdog timer: 1 channel on-chip power-on-clear circuit on-chip bit sequential buffer power supply voltage: v dd = 1.8 to 3.6 v operating ambient temperature: t a = ? 40 to +85 c 2.2 applications keyless entry and other autom otive electrical equipment. 2.3 ordering information part number package internal rom pd789861mc- -5a4 20-pin plastic ssop (7.62 mm (300)) mask rom pd78e9861amc-5a4 20-pin plastic ssop (7.62 mm (300)) eeprom remark indicates rom code suffix.
chapter 2 general ( pd789861 subseries) user?s manual u14826ej4v0ud 29 2.4 pin configuration (top view) 20-pin plastic ssop (7.62 mm (300)) pd789861mc- -5a4 pd78e9861amc-5a4 reset cl1 cl2 v ss ic (v pp ) v dd p00 p01 p02 p03 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 p21/tmi p20/tmo/bsfo p07 p06 p05 p04 p43/kr13 p42/kr12 p41/kr11 p40/kr10 caution connect the ic (internally connected) pin directly to v ss . remark pin connections in parenthes es are intended for the pd78e9861a. bsfo: bit sequential buffer output reset: reset cl1, cl2: rc oscillator tmi: timer input ic: internally connected tmo: timer output kr10 to kr13: key return v dd : power supply p00 to p07: port 0 v pp : programming power supply p20, p21: port 2 v ss : ground p40 to p43: port 4
chapter 2 general ( pd789861 subseries) user?s manual u14826ej4v0ud 30 2.5 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. 80-pin sio, 8-bit a/d converter, and resistance division type lcd (28 4) 52-pin 52-pin sio and resistance division type lcd (24 4) 8-bit a/d and on-chip voltage booster type lcd (23 4) pd789327 pd789467 pd789446 pd789436 pd789426 pd789306 pd789316 pd789426 with enhanced a/d converter (10 bits) pd789446 with enhanced a/d converter (10 bits) sio, 8-bit a/d, and on-chip voltage booster type lcd (15 4) sio, 8-bit a/d, and on-chip voltage booster type lcd (5 4) rc oscillation version of the pd789306 sio and on-chip voltage booster type lcd (24 4) 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin pd789407a pd789456 lcd drive 80-pin pd789417a pd789407a with enhanced a/d converter (10 bits) sio, 10-bit a/d converter, and on-chip voltage booster type lcd (28 4) 80-pin sio, 8-bit a/d converter, and resistance division type lcd (28 4) 80-pin pd789478 pd789488 pd789881 64-pin uart and resistance division type lcd (26 4) products under development products in mass production pd789014 small-scale package, general-purpose applications 78k/0s series 28-pin pd789014 with enhanced timer and increased rom, ram capacity on-chip uart and capable of low voltage (1.8 v) operation pd789074 with added subsystem clock pd789146 pd789156 44-pin small-scale package, general-purpose applications and a/d converter 44-pin 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789177 pd789167 30-pin 30-pin pd789104a pd789114a pd789167 with enhanced a/d converter (10 bits) pd789104a with enhanced timer pd789124a with enhanced a/d converter (10 bits) rc oscillation version of the pd789104a pd789104a with enhanced a/d converter (10 bits) pd789026 with added 8-bit a/d converter and multiplier pd789104a with added eeprom pd789146 with enhanced a/d converter (10 bits) pd789177y pd789167y y subseries products support smb. 88-pin pd789830 pd789835 144-pin uart and dot lcd (40 16) uart, 8-bit a/d, and dot lcd (total display output pins: 96) 42-/44-pin 44-pin pd789074 30-pin pd789026 with enhanced timer 30-pin pd789074 with enhanced timer and increased rom, ram capacity pd789088 pd789046 pd789026 usb 44-pin pd789800 for pc keyboard and on-chip usb function inverter control 44-pin pd789842 on-chip inverter controller and uart vfd drive 52-pin pd789871 on-chip vfd controller (total display output pins: 25) keyless entry 20-pin pd789860 pd789861 20-pin on-chip poc and key return circuit rc oscillation version of the pd789860 on-chip bus controller pd789850a on-chip can controller meter control pd789052 20-pin pd789860 without eeprom, poc, and lvi pd789062 20-pin rc oscillation version of the pd789052 pd789862 30-pin 30-pin 44-pin pd789860 with enhanced timer, added sio, and increased rom, ram capacity pd789852 pd789850a with enhanced functions such as timer and a/d converter remark vfd (vacuum fluorescent display) is referred to as fip (fluorescent indicator panel) in some documents, but the functions of the two are the same.
chapter 2 general ( pd789861 subseries) user?s manual u14826ej4v0ud 31 the major functional differences bet ween the subseries are listed below. series for general-purpose applications and lcd drive timer v dd function subseries name rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remarks pd789046 16 kb 1 ch pd789026 4 kb to 16 kb 1 ch 34 pd789088 16 kb to 32 kb 3 ch pd789074 2 kb to 8 kb 1 ch 1 ch 24 pd789014 2 kb to 4 kb 1 ch (uart: 1 ch) 22 ? pd789062 rc oscillation version small-scale package, general- purpose applications pd789052 4 kb 2 ch ? ? 1 ch ? ? ? 14 1.8 v ? pd789177 ? 8 ch pd789167 16 kb to 24 kb 3 ch 1 ch 8 ch ? 31 ? pd789156 ? 4 ch pd789146 8 kb to 16 kb 4 ch ? on-chip eeprom pd789134a ? 4 ch pd789124a 4 ch ? rc oscillation version pd789114a ? 4 ch small-scale package, general- purpose applications and a/d converter pd789104a 2 kb to 8 kb 1 ch 1 ch ? 1 ch 4 ch ? 1 ch (uart: 1 ch) 20 1.8 v ? pd789835 24 kb to 60 kb 6 ch ? 3 ch 37 1.8 v note pd789830 24 kb 1 ch ? 1 ch (uart: 1 ch) 30 2.7 v dot lcd supported pd789488 32 kb to 48 kb ? 8 ch pd789478 24 kb to 48 kb 8 ch ? 2 ch (uart: 1 ch) 45 pd789417a ? 7 ch pd789407a 12 kb to 24 kb 3 ch 7 ch ? 43 pd789456 ? 6 ch pd789446 6 ch ? 30 pd789436 ? 6 ch pd789426 12 kb to 16 kb 6 ch 1 ch (uart: 1 ch) 40 ? pd789316 rc oscillation version pd789306 8 kb to 16 kb 1 ch ? 2 ch (uart: 1 ch) 23 pd789467 1 ch ? 18 lcd drive pd789327 4 kb to 24 kb 2 ch ? 1 ch 1 ch ? ? 1 ch 21 1.8 v ? note flash memory version: 3.0 v
chapter 2 general ( pd789861 subseries) user?s manual u14826ej4v0ud 32 series for assp timer v dd function subseries name rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remarks usb pd789800 8 kb 2 ch ? ? 1 ch ? ? 2 ch (usb: 1 ch) 31 4.0 v ? inverter control pd789842 8 kb to 16 kb 3 ch note 1 1 ch 1 ch 8 ch ? 1 ch (uart: 1 ch) 30 4.0 v ? pd789852 24 kb to 32 kb 3 ch ? 8 ch 3 ch (uart: 2 ch) 31 on-chip bus controller pd789850a 16 kb 1 ch 1 ch ? 1 ch 4 ch ? 2 ch (uart: 1 ch) 18 4.0 v ? pd789861 rc oscillation version, on- chip eeprom pd789860 4 kb 2 ch ? ? 14 keyless entry pd789862 16 kb 1 ch 2 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 22 1.8 v on-chip eeprom vfd drive pd789871 4 kb to 8 kb 3 ch ? 1 ch 1 ch ? ? 1 ch 33 2.7 v ? meter control pd789881 16 kb 2 ch 1 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 28 2.7 v note 2 ? notes 1. 10-bit timer: 1 channel 2. flash memory version: 3.0 v
chapter 2 general ( pd789861 subseries) user?s manual u14826ej4v0ud 33 2.6 block diagram port 0 p00 to p07 port 2 p20, p21 v dd v ss ic (v pp ) tmi/p21 watchdog timer system control reset cl1 cl2 port 4 p40 to p43 78k/0s cpu core rom 8-bit timer/ event counter 40 8-bit timer 30 cascaded 16-bit timer counter tmo/p20 bit seq. buffer ram eeprom key return 10 kr10/p40 to kr13/p43 power on clear power on clear low voltage indicator bsfo/p20 remark pin connections in parenthes es are intended for the pd78e9861a.
chapter 2 general ( pd789861 subseries) user?s manual u14826ej4v0ud 34 2.7 overview of functions part number item pd789861 pd78e9861a mask rom eeprom rom 4 kb high-speed ram 128 bytes internal memory eeprom 32 bytes oscillator rc oscillator minimum instruction execution time 2.0/8.0 s (@1.0 mhz operation with system clock) general-purpose registers 8 bits 8 registers instruction set 16-bit operations bit manipulations (such as set, reset, and test) i/o ports total: 14 cmos i/o: 10 cmos input: 4 timers 8-bit timer: 2 channels watchdog timer: 1 channel poc circuit generates internal reset signal according to co mparison of detection voltage to power supply voltage power-on-clear circuit lvi circuit generates interrupt request signal according to comparison of detection voltage to power supply voltage bit sequential buffer 8 bits 8 bits = 16 bits key return function generates key return signal according falling edge detection maskable internal: 5 vectored interrupt sources non-maskable internal: 1, external: 1 power supply voltage v dd = 1.8 to 3.6 v operating ambient temperature t a = ? 40 to + 85c package 20-pin plastic ssop (7.62 mm (300))
user?s manual u14826ej4v0ud 35 chapter 3 pin functions 3.1 pin function list (1) port pins pin name i/o function after reset alternate function p00 to p07 i/o port 0 8-bit i/o port input/output can be specified in 1-bit units. input kr0 to kr3 p20 tmo/bsfo p21 i/o port 2 2-bit i/o port input/output can be specified in 1-bit units. input tmi p40 to p43 input port 4 4-bit input-only port for mask rom versions, an on-chip pull-up resistor can be specified by means of the mask option. input kr10 to kr13 (2) non-port pins pin name i/o function after reset alternate function tmi input 8-bit timer (tm40) i nput input p21 tmo output 8-bit timer (tm40) output input p20/bsfo bsfo output bit sequential buffer (bsf10) output input p20/tmo kr10 to kr13 input key return input input p40 to p43 x1 note 1 input ? ? x2 note 1 ? connecting ceramic/crystal resonator for system clock oscillation ? ? cl1 note 2 input ? ? cl2 note 2 ? connecting resistor (r) and capacitor (c) for system clock oscillation ? ? reset input system reset input input ? v dd ? positive supply voltage ? ? v ss ? ground potential ? ? ic ? internally connected. connect directly to v ss . ? ? v pp ? this pin is used to set the eeprom programming mode and applies a high voltage when a program is written or verified. ? ? notes 1. pd789860 subseries only 2. pd789861 subseries only
chapter 3 pin functions user?s manual u14826ej4v0ud 36 3.2 description of pin functions 3.2.1 p00 to p07 (port 0) these pins constitute an 8-bit i/o port and can be set to i nput or output port mode in 1- bit units by using port mode register 0 (pm0). 3.2.2 p20, p21 (port 2) these pins constitute a 2-bit i/o port. in addition, thes e pins function as the time r input/output and bit sequential buffer output. port 2 can be set to the following operation modes in 1-bit units. (1) port mode in port mode, p20 and p21 function as a 2-bit i/o port. po rt 2 can be set to input or output port mode in 1-bit units by using port mode register 2 (pm2). (2) control mode in this mode, p20 and p21 function as the time r input/output and the bit sequential buffer output. (a) bsfo this is the output pin of the bit sequential buffer. (b) tmi this is the external clock input pin for the timer 40. (c) tmo this is the output pin of the timer 40. 3.2.3 p40 to p43 (port 4) these pins constitute a 4-bit input-only port. in addi tion, these pins function as the key return input. (1) port mode in port mode, p40 to p43 function as a 4-bit input -only port. for mask rom versions, an on-chip pull-up resistor can be specified by means of the mask option. (2) control mode in this mode, p40 to p43 function as the key return input (kr10 to kr13). 3.2.4 reset an active-low system reset si gnal is input to this pin. 3.2.5 x1, x2 ( pd789860 subseries) these pins are used to connect a crystal resonator for system clock oscillation. to supply an external clock, input the clo ck to x1 and input the inverted signal to x2. 3.2.6 cl1, cl2 ( pd789861 subseries) these pins are used to connect a resistor (r) and capacitor (c) for system clock oscillation. to supply an external clock, input the clock to cl1 and input the inverted signal to cl2.
chapter 3 pin functions user?s manual u14826ej4v0ud 37 3.2.7 v dd this pin supplies positive power. 3.2.8 v ss this pin is the ground potential pin. 3.2.9 v pp ( pd78e9860a, 78e9861a only) a high voltage should be applied to this pin when the eeprom programming mode is set and when the program is written or verified. perform either of the following pin handling. ? individually connect a 10 k ? pull-down resistor. ? connect to a dedicate flash programmer in the programming mode and directly to v ss in the normal operation mode by using a jumper on the board. if the wiring length between the v pp and v ss pins is too long or if exter nal noise is superimposed on the v pp pin, your program may not be executed correctly. 3.2.10 ic (mask rom version only) the ic (internally connected) pin is used to set the pd789860 and 789861 to test mode before shipment. in normal operation mode, directly connect this pin to the v ss pin with as short a wiring length as possible. if a potential difference is generat ed between the ic pin and the v ss pin due to a long wiring length between these pins or an external noise superimposed on the ic pin, the user program may not run correctly. ? directly connect the ic pin to the v ss pin. v ss ic keep short
chapter 3 pin functions user?s manual u14826ej4v0ud 38 3.3 pin i/o circuits and recomme nded connection of unused pins the i/o circuit type of each pin and recommended connecti on of unused pins are shown in table 3-1. for the i/o circuit configuration of each type, see figure 3-1 . table 3-1. types of pin i/o circuits a nd recommended connection of unused pins pin name i/o circuit type i/o re commended connection of unused pins p00 to p07 5 p20/tmo/bsfo p21/tmi 8 input: independently connect to v dd or v ss via a resistor. output: leave open. p40/kr10 to p43/kr13 (mask rom version) 2-e p40/kr10 to p43/kr13 ( pd78e9860a, 78e9861a) connect directly to v dd . reset 2 i/o ? ic connect directly to v ss . v pp ? ? independently connect to a 10 k ? pull-down resistor or connect directly to v ss . figure 3-1. pin i/o circuits schmitt-triggered input with hysteresis characteristics type 2 in type 2-e data output disable input enable v dd p-ch in/out n-ch v ss data output disable v dd p-ch in/out n-ch v ss type 5 type 8 v dd pull-up resistor (mask option) in
user?s manual u14826ej4v0ud 39 chapter 4 cpu architecture 4.1 memory space the pd789860, 789861 subseries can each access up to 64 kb of memory space. figures 4-1 and 4-2 show the memory maps. figure 4-1. memory map ( pd789860, 789861) special function registers (sfr) 256 8 bits internal high-speed ram 128 8 bits reserved internal rom 4,096 8 bits program memory space data memory space program area program area callt table area vector table area reserved eeprom (data memory) 32 8 bits ffffh 0fffh 0080h 007fh 0040h 003fh 000eh 000dh 0000h ff00h feffh fe80h fe7fh f820h f81fh f800h f7ffh 1000h 0fffh 0000h
chapter 4 cpu architecture user?s manual u14826ej4v0ud 40 figure 4-2. memory map ( pd78e9860a, 78e9861a) special function registers (sfr) 256 8 bits internal high-speed ram 128 8 bits reserved eeprom (program memory) 4,096 8 bits program memory space data memory space program area program area callt table area vector table area reserved eeprom (data memory) 32 8 bits ffffh 0fffh 0080h 007fh 0040h 003fh 000eh 000dh 0000h ff00h feffh fe80h fe7fh f820h f81fh f800h f7ffh 1000h 0fffh 0000h
chapter 4 cpu architecture user?s manual u14826ej4v0ud 41 4.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). the pd789860, 789861 subseries provide the following inter nal roms (or eeprom) containing the following capacities. table 4-1. internal rom capacity internal rom part number structure capacity pd789860, 789861 mask rom pd78e9860a, 78e9861a eeprom 4,096 8 bits the following areas are allocated to t he internal program memory space: (1) vector table area the 14-byte area of addresses 0000h to 000dh is reserv ed as a vector table ar ea. this area stores program start addresses to be used when branching by r eset input or interrupt request generation. of a 16-bit address, the lower 8 bits are stored in an ev en address, and the higher 8 bits are stored in an odd address. table 4-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 0008h inttm40 0002h intkr1 000ah intlvi1 0004h intwdt 000ch intee0 0006h inttm30 (2) callt instruction table area the subroutine entry address of a 1-byte call instruction (callt) can be stored in the 64-byte area of addresses 0040h to 007fh. 4.1.2 internal data memory space the pd789860, 789861 subseries provide the following rams. (1) internal high-speed ram the internal high-speed ram is provided in the area of fe80h to feffh. the internal high-speed ram can also be used as a stack memory. (2) eeprom the eeprom is provided in t he area of f800h to f81fh. for details of eeprom, see chapter 5 eeprom (data memory) .
chapter 4 cpu architecture user?s manual u14826ej4v0ud 42 4.1.3 special function register (sfr) area special function registers (sfrs) of on-chip peripheral hardware are allocat ed to the area of ff00h to ffffh (see table 4-3 ). 4.1.4 data memory addressing each of the pd789860, 789861 subseries is provided with a wide range of addressing modes to make memory manipulation as efficient as possibl e. the data memory area (fe80h to ffffh) can be accessed using a unique addressing mode according to its use, such as a special f unction register (sfr). figur es 4-3 and 4-4 illustrate the data memory addressing. figure 4-3. data memory addressing ( pd789860, 789861) special function registers (sfr) 256 8 bits internal high-speed ram 128 8 bits reserved internal rom 4,096 8 bits direct addressing register indirect addressing based addressing sfr addressing short direct addressing reserved eeprom 32 8 bits ffffh ff00h feffh ff20h fe1fh fe80h fe7fh f820h f81fh f800h f7ffh 1000h 0fffh 0000h
chapter 4 cpu architecture user?s manual u14826ej4v0ud 43 figure 4-4. data memory addressing ( pd78e9860a, 78e9861a) special function registers (sfr) 256 8 bits internal high-speed ram 128 8 bits reserved eeprom (program memory) 4,096 8 bits direct addressing register indirect addressing based addressing sfr addressing short direct addressing reserved eeprom (data memory) 32 8 bits ffffh ff00h feffh ff20h fe1fh fe80h fe7fh f820h f81fh f800h f7ffh 1000h 0fffh 0000h
chapter 4 cpu architecture user?s manual u14826ej4v0ud 44 4.2 processor registers the pd789860, 789861 subseries provide the follo wing on-chip processor registers: 4.2.1 control registers the control registers have special f unctions to control the program sequenc e statuses and stack memory. the control registers include a pr ogram counter, a program stat us word, and a stack pointer. (1) program counter (pc) the program counter is a 16-bit r egister which holds the address info rmation of the next program to be executed. in normal operation, the pc is automat ically incremented according to the num ber of bytes of the instruction to be fetched. when a branch instruct ion is executed, immediate data or register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 4-5. program counter configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit r egister consisting of various flags to be set/reset by instruction execution. program status word contents ar e automatically stacked upon interr upt request generation or push psw instruction execution and ar e automatically restored upon execution of the reti and pop psw instructions. reset input sets psw to 02h. figure 4-6. program status word configuration 70 ie z 0 ac 0 0 1 cy psw (a) interrupt enable flag (ie) this flag controls interrupt request acknowledge operations of the cpu. when ie = 0, the interrupt disabled (d i) status is set. all interrupt requests except non-maskable interrupt are disabled. when ie = 1, the interrupt enabled (ei) status is set. interrupt reques t acknowledgment is controlled with an interrupt mask flag for various interrupt sources. this flag is reset to 0 upon di instruction executi on or interrupt acknowledgment and is set to 1 upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set to 1. it is reset to 0 in all other cases. (c) auxiliary carry flag (ac) if the operation result has a carry from bi t 3 or a borrow at bit 3, this flag is set to 1. it is reset to 0 in all other cases.
chapter 4 cpu architecture user?s manual u14826ej4v0ud 45 (d) carry flag (cy) this flag stores overflow and underfl ow that have occurred upon add/subtra ct instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruct ion execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of t he memory stack area. only the internal high-speed ram area can be set as the stack area. figure 4-7. stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented befor e writing (saving) to the stack me mory and is incremented after reading (restoring) from the stack memory. each stack operation saves/restores dat a as shown in figures 4-8 and 4-9. caution since reset input makes sp contents undefi ned, be sure to initialize the sp before instruction execution. figure 4-8. data to be saved to stack memory interrupt psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower half register pairs sp sp _ 2 sp _ 2 call, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 upper half register pairs figure 4-9. data to be restored from stack memory reti instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower half register pairs ret instruction pop rp instruction sp pc7 to pc0 upper half register pairs sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3
chapter 4 cpu architecture user?s manual u14826ej4v0ud 46 4.2.2 general-purpose registers a general-purpose register consists of eight 8-bit registers (x, a, c, b, e, d, l, and h). in addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (ax, bc, de, and hl). registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). figure 4-10. general-purpo se register configuration (a) absolute names r0 15 0 7 0 16-bit processing 8-bit processing rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 (b) function names x 15 0 7 0 16-bit processing 8-bit processing hl de bc ax a c b e d l h
chapter 4 cpu architecture user?s manual u14826ej4v0ud 47 4.2.3 special function registers (sfrs) unlike the general-purpose register s, each special function regist er has a special function. the special function registers are alloca ted to the 256-byte area ff00h to ffffh. the special function register s can be manipulated, like t he general-purpose registers, with operation, transfer, and bit manipulation instructions. manipulatable bit units (1 , 8, and 16) differ depending on the special function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describes a symbol reserved by the assembler for the 1- bit manipulation instructi on operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describes a symbol reserved by the assembler for the 8-bit manipulation instruct ion operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describes a symbol reserved by the assembler for the 16-bit manipulation instruct ion operand. when specifying an address, describe an even address. table 4-3 lists the special function r egisters. the meanings of the symbol s in this table are as follows: ? symbol indicates the addresses of the implem ented special function registers. t he symbols shown in this column are reserved words in the assembler, and have already been defined in a header file called ?sfrbit.h? in the c compiler. therefore, t hese symbols can be used as instruction oper ands if an assembler or integrated debugger is used. ? r/w indicates whether the special functi on register can be read or written. r/w: read/write r: read only w: write only ? number of bits manipulated simultaneously indicates the bit units (1, 8, and 16) in which the special function regi ster can be manipulated. ? after reset indicates the status of the special function register when the reset signal is input.
chapter 4 cpu architecture user?s manual u14826ej4v0ud 48 table 4-3. special function registers number of bits manipulated simultaneously address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 ? ff02h port 2 p2 r/w ? ff04h port 4 p4 r ? 00h ff10h bit sequential buffer 10 data register l bsfrl10 ? ff11h bit sequential buffer 10 data register h bsfrh10 w ? note 1 undefined ff20h port mode register 0 pm0 ? ff22h port mode register 2 pm2 ? ffh ff42h timer clock sele ction register 2 tcl2 r/w ? ? 00h ff50h 8-bit compare register 30 cr30 w ? ? undefined ff51h 8-bit timer counter 30 tm30 r ? ? ff52h 8-bit timer mode control register 30 tmc30 r/w ? 00h ff53h 8-bit compare register 40 cr40 ? ? ff54h 8-bit compare register h40 crh40 w ? ? undefined ff55h 8-bit timer counter 40 tm40 r ? ? ff56h 8-bit timer mode control register 40 tmc40 r/w ? ff57h carrier generator output control register 40 tca40 w ? ? ff60h bit sequential buffer output control register 10 bsfc10 ? 00h ffd8h eeprom write control register 10 eewc10 ? 08h ffddh power-on-clear register 1 pocf1 ? 00h note 2 ffdeh low-voltage detection register 1 lvif1 ? ffdfh low-voltage detection level selection register 1 lvis1 ? ffe0h interrupt request flag register 0 if0 ? 00h ffe4h interrupt mask flag register 0 mk0 ? ffh fff9h watchdog timer mode register wdtm ? 00h fffah oscillation stabilization time selection register note 3 osts ? ? 04h fffbh processor clock control register pcc r/w ? 02h notes 1. specify address ff10h directly for 16-bit access. 2. this value is 04h only after a power-on-clear reset. 3. pd789860 subseries only
chapter 4 cpu architecture user?s manual u14826ej4v0ud 49 4.3 instruction address addressing an instruction address is determined by the program counter (p c) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an in struction to be fetched each time another instruction is executed. when a branch instruction is ex ecuted, the branch destination address information is set to the pc to branch by the following addressing (for details of eac h instruction, refer to 78k/0s series instructions user?s manual (u11047e) ). 4.3.1 relative addressing [function] the value obtained by adding 8-bit immediat e data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (p c) to branch. the displacement value is treated as signed two?s complement data (?128 to +127) and bit 7 becomes the sign bit. in other words, the range of branch in relative addressing is betw een ?128 and +127 of the start address of the following instruction. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 876 jdisp8 when s = 0, indicates that all bits are ?0?. ... pc is the start address of the next instruction of a br instruction. when s = 1, indicates that all bits are ?1?.
chapter 4 cpu architecture user?s manual u14826ej4v0ud 50 4.3.2 immediate addressing [function] immediate data in the instructi on word is transferred to the pr ogram counter (pc) to branch. this function is carried out when the call !addr 16 and br !addr16 instruct ions are executed. call !addr16 and br !addr16 instru ctions can be used to branch to all the memory spaces. [illustration] in case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. 4.3.3 table indirect addressing [function] the table contents (branch des tination address) of the particular locati on to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are tr ansferred to the program counter (pc) to branch. table indirect addressing is carried out when the callt [addr5] inst ruction is executed. this instruction can be used to branch to all the memory spaces according to the address stored in the me mory table 40h to 7fh. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 0 01 765 10 ta 4?0 instruction code
chapter 4 cpu architecture user?s manual u14826ej4v0ud 51 4.3.4 register addressing [function] the register pair (ax) contents to be specified with an instruction word ar e transferred to the program counter (pc) to branch. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 4 cpu architecture user?s manual u14826ej4v0ud 52 4.4 operand address addressing the following methods (addressing) are available to s pecify the register and memo ry to undergo manipulation during instruction execution. 4.4.1 direct addressing [function] the memory indicated by immediate data in an instruction word is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h instruction code 0 0 1 0 1 0 0 1 op code 0 0 0 0 0 0 0 0 00h 1 1 1 1 1 1 1 0 feh [illustration] 70 op code addr16 (low) addr16 (high) memory
chapter 4 cpu architecture user?s manual u14826ej4v0ud 53 4.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is dire ctly addressed with the 8-bit data in an instruction word. the fixed space where this addressing is applied is t he 256-byte space fe20h to ff1fh. an internal high- speed ram is mapped at fe20h to feffh and the specia l function registers (sfr ) are mapped at ff00h to ff1fh. the sfr area where short direct addressi ng is applied (ff00h to ff1fh) is a par t of the total sfr area. in this area, ports which are frequently access ed in a program and a compare register of the timer counter are mapped, and these sfrs can be mani pulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an e ffective address is cleared to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh i mmediate data (even address only) [description example] mov fe90h, #50h; when setting saddr to fe90h and the immediate data to 50h instruction code 1 1 1 1 0 1 0 1 op code 1 0 0 1 0 0 0 0 90h (saddr-offset) 0 1 0 1 0 0 0 0 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 8 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0. when 8-bit immediate data is 00h to 1fh, = 1.
chapter 4 cpu architecture user?s manual u14826ej4v0ud 54 4.4.3 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addre ssed with the 8-bit immediat e data in an instruction word. this addressing is applied to the 256-byte space ff 00h to ffffh. however, sfrs mapped at ff00h to ff1fh can also be accessed with short direct addressing. [operand format] identifier description sfr special function register name [description example] mov pm0, a; when selecting pm0 for sfr instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
chapter 4 cpu architecture user?s manual u14826ej4v0ud 55 4.4.4 register addressing [function] a general-purpose register is accessed as an operand. the general-purpose register to be acce ssed is specified with t he register specify c ode and functional name in the instruction code. register addressing is carried out when an instruction with the following operand forma t is executed. when an 8-bit register is specified, one of the eight registers is specified wit h 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ?r? and ?rp? can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting the c register for r instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 register specify code incw de; when selecting the de register pair for rp instruction code 1 0 0 0 1 0 0 0 register specify code
chapter 4 cpu architecture user?s manual u14826ej4v0ud 56 4.4.5 register indirect addressing [function] the memory is addressed with the contents of the r egister pair specified as an oper and. the register pair to be accessed is specified with t he register pair specify code in the instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code 0 0 1 0 1 0 1 1 [illustration] 15 0 8 d 7 e 0 7 7 0 a de the contents of addressed memory are transferred memory address specified by register pair de
chapter 4 cpu architecture user?s manual u14826ej4v0ud 57 4.4.6 based addressing [function] 8-bit immediate data is added to the cont ents of the base register, that is, t he hl register pair, and the sum is used to address the memory. addition is performed by ex panding the offset data as a pos itive number to 16 bits. a carry from the 16th bit is ignored. this addre ssing can be carried out for all the memory spaces. [operand format] identifier description ? [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 4.4.7 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subrout ine call, and return instructions are executed or the register is sav ed/restored upon interrupt request generation. stack addressing can be used to access t he internal high-speed ram area only. [description example] in the case of push de instruction code 1 0 1 0 1 0 1 0
user?s manual u14826ej4v0ud 58 chapter 5 eeprom (data memory) 5.1 memory space besides internal high-speed ram, the pd789860, 789861 subseries have 32 8 bits of electrically erasable prom (eeprom) on-chip as data memory. unlike normal ram, eeprom can maintain its contents ev en if its power supply is cut. in addition, unlike eprom, its contents can be electrically erased without using ultraviolet rays. 5.2 eeprom configuration eeprom consists of the eeprom itself and a control section. the control section consists of eepr om write control register 10 (eewc 10) which controls eeprom writing and a part that detects the terminat ion of writing and generates an in terrupt request signal (intee0). figure 5-1. eeprom block diagram data latch eeprom (32 8 bits) read/write controller eeprom timer prescaler intee0 eeprom write control register 10 (eewc10) ewcs102 ewcs101 ewcs100 ewst10 ere10 ewe10 f x /2 3 to f x /2 8 8-bit timer 40 output address latch internal bus 5.3 eeprom control register eeprom is controlled by eeprom writ e control register 10 (eewc10). eewc10 is the register that sets the eeprom c ount clock selection, and eeprom write control. eewc10 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 08h. figure 5-2 shows the format of eeprom write control regist er 10. tables 5-1 and 5-2 show eeprom write times.
chapter 5 eeprom (data memory) user?s manual u14826ej4v0ud 59 figure 5-2. format of eeprom write control register 10 symbol 7 6 5 4 3 <2> <1> <0> address after reset r/w eewc10 0 ewcs102 ewcs101 ewcs100 1 er e10 ewst10 ewe10 ffd8h 08h r/w note eeprom timer count clock selection ewcs102 ewcs101 ewcs100 when operating at f x = 5.0 mhz when operating at f cc = 1.0 mhz 0 0 0 f x /2 3 (625 khz) f cc /2 3 (125 khz) 0 0 1 f x /2 4 (313 khz) f cc /2 4 (62.5 khz) 0 1 0 f x /2 5 (156 khz) f cc /2 5 (31.3 khz) 0 1 1 f x /2 6 (78.1 khz) f cc /2 6 (15.6 khz) 1 0 0 f x /2 7 (39.1 khz) f cc /2 7 (7.81 khz) 1 0 1 f x /2 8 (19.5 khz) f cc /2 8 (3.91 khz) 1 1 0 output of 8-bit timer 40 1 1 1 setting prohibited ere10 ewe10 write read remarks 0 0 disabled disabled eeprom is in standby state (low power consumption mode) 0 1 setting prohibited 1 0 disabled enabled 1 1 enabled enabled ewst10 eeprom write status flag 0 not writing to eeprom (eeprom can be read or writt en. however, writing is disabled if ewe10 = 0.) 1 writing to eeprom (eeprom cannot be read or written.) note bit 1 is read only. caution be sure to clear bit 3 to 1 and bit 7 to 0. remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : system clock oscillation frequency (rc oscillation)
chapter 5 eeprom (data memory) user?s manual u14826ej4v0ud 60 table 5-1. eeprom write time (when operating at f x = 5.0 mhz) ewcs102 ewcs101 ewcs100 eeprom timer c ount clock eeprom data write time note 1 0 0 0 f x /2 3 (625 khz) 2 3 /f x 145 (setting prohibited) note 2 0 0 1 f x /2 4 (313 khz) 2 4 /f x 145 (setting prohibited) note 2 0 1 0 f x /2 5 (156 khz) 2 5 /f x 145 (setting prohibited) note 2 0 1 1 f x /2 6 (78.1 khz) 2 6 /f x 145 (setting prohibited) note 2 1 0 0 f x /2 7 (39.1 khz) 2 7 /f x 145 (3.71 ms) 1 0 1 f x /2 8 (19.5 khz) 2 8 /f x 145 (setting prohibited) note 2 1 1 0 output of 8-bit timer 40 output of 8-bit timer 40 145 1 1 1 setting prohibited notes 1. be sure to set the eeprom write ti me within the range of 3.3 to 6.6 ms. 2. during operation at f x = 5.0 mhz, setting is prohibited bec ause the condition that an eeprom write time must be between 3.3 and 6. 6 ms is not satisfied. remark f x : system clock oscillation frequency (ceramic/crystal oscillation) table 5-2. eeprom write time (when operating at f cc = 1.0 mhz) ewcs102 ewcs101 ewcs100 eeprom timer c ount clock eeprom data write time note 1 0 0 0 f cc /2 3 (125 khz) 2 3 /f cc 145 (setting prohibited) note 2 0 0 1 f cc /2 4 (62.5 khz) 2 4 /f cc 145 (setting prohibited) note 2 0 1 0 f cc /2 5 (31.3 khz) 2 5 /f cc 145 (4.64 ms) 0 1 1 f cc /2 6 (15.6 khz) 2 6 /f cc 145 (setting prohibited) note 2 1 0 0 f cc /2 7 (7.81 khz) 2 7 /f cc 145 (setting prohibited) note 2 1 0 1 f cc /2 8 (3.91 khz) 2 8 /f cc 145 (setting prohibited) note 2 1 1 0 output of 8-bit timer 40 output of 8-bit timer 40 145 1 1 1 setting prohibited notes 1. be sure to set the eeprom write ti me within the range of 3.3 to 6.6 ms. 2. during operation at f cc = 1.0 mhz, setting is prohibited bec ause the condition that an eeprom write time must be between 3.3 and 6. 6 ms is not satisfied. remark f cc : system clock oscillation frequency (rc oscillation)
chapter 5 eeprom (data memory) user?s manual u14826ej4v0ud 61 5.4 notes for eeprom writing the following caution points pertain to writing to eeprom. (1) when fetching an instruction from eeprom or stopping the system clock oscillator, be sure to do so after setting eeprom to write-disabled (ewe10 = 0). (2) set the count clock in a state in which the selected clock is operating (o scillating). if the selected count clock is stopped, there is no transit ion to the state in which writing is possible even if the clock operation is subsequently started and eeprom is set to write-enabled (ewe10 = 1). (3) be sure to set the eeprom write ti me within the range of 3.3 to 6.6 ms. (4) when setting ere10 and ewe10, be sure to use the fo llowing procedure. if you se t these using other than the following procedure, there is no transition to the state in which writing to eeprom is possible. <1> set ere10 to 1 (in a state in which ewe10 = 0) <2> set ewe10 to 1 (in a state in which ere10 = 1) <3> wait 1 ms or more using software <4> shift to state in which writing to eeprom is possible ere10 a b c ewe10 d 1 ms or more a (ere10 = 1): transition to state in which reading is possible b (ewe10 = 1): set count clock before this point. c: transition to state in which writing is possible d: when ere10 is cleared (ere10 = 0), ewe10 is also cleared (ewe10 = 0). reading or writing is not possible in this state. (5) when performing a write to eeprom, execut e it after confirming that ewst10 = 0. if a write is executed to eeprom when ew st10 = 1, the instruction is ignored.
chapter 5 eeprom (data memory) user?s manual u14826ej4v0ud 62 (6) do not execute the following oper ations while writing to eeprom, as execution will cause the eeprom cell value at that addre ss to become undefined. turn off the power execute a reset clear ere10 to 0 clear ewe10 to 0 switch the eeprom timer count clock (7) do not execute the following operat ion while writing to eeprom after se lecting system clock division for the eeprom timer count clock, as execution will cause the eeprom cell value at that address to become undefined. execute a stop instruction (8) do not execute the following operati ons while writing to eeprom after se lecting 8-bit timer 40 output for the eeprom timer count clock, as execution will cause the eeprom cell value at that address to become undefined. execute a stop instruction stop 8-bit timer 40 timer output stop 8-bit timer 40 operation (9) do not execute the followi ng operations while writing to or reading from eeprom, as execution will cause the eeprom data read next to become undefined, and a cp u inadvertent program loop could result. clear ere10 to 0 execute a write to eeprom (10) when not writing to or reading fr om eeprom, it is possible to enter lo w-power consumption mode by clearing ere10 to 0. in the ere10 = 1 st ate, a current of about 0.27 ma (v dd = 3.6 v) is always flowing. if an instruction to read from eeprom is then executed, a further 0.9 ma cu rrent will flow, increasing the total current flow at this time to approximately 1.17 ma (v dd = 3.6 v). in the ere10 = 1, ewe10 = 1 st ate, a current of about 0.3 ma (v dd = 3.6 v) is always flowing. if an instruction to write to eeprom is then executed, a further 0.7 ma current will flow, and if an instruction to read from eeprom is executed, a further 0.9 ma current will flow, increasing the total current flow at this time to approximately 1.0 ma (v dd = 3.6 v) for the former case and 1.2 ma (v dd = 3.6 v) for the latter. (11) execution of a stop instructi on causes an automatic change to low-pow er consumption m ode, regardless of the ere10 and ewe10 settings. the st ates of ere10 and ewe10 at the ti me are maintained. during the wait time following stop mode rel ease, a current of approximately 300 a (v dd = 3.6 v) flows. executing a halt instruction does not c hange the mode to low-power consumption mode.
user?s manual u14826ej4v0ud 63 chapter 6 port functions 6.1 port functions the pd789860, 789861 subseries is provided wit h the ports shown in table 6- 1. these ports enable several types of control. these ports, while originally designed as digital input/out put ports, have alternate func tions. for the alternate functions, see chapter 3 pin functions . table 6-1. port functions name pin name function port 0 p00 to p07 i/o port. input/out put can be specified in 1-bit units. port 2 p20, p21 i/o port. input/out put can be specified in 1-bit units. port 4 p40 to p43 input-only port. mask rom ve rsions can specify an on- chip pull-up resistor by means of the mask option. 6.2 port configuration ports include the following hardware. table 6-2. configuration of port item configuration control registers port mode registers (pmm: m = 0, 2) ports total: 14 (cmos i/o: 10, cmos input: 4) pull-up resistors mask rom version: 4 (mask option control only) eeprom version: none
chapter 6 port functions user?s manual u14826ej4v0ud 64 6.2.1 port 0 this is an 8-bit i/o port with an output latc h. port 0 can be set to input or out put mode in 1-bit units by using port mode register 0 (pm0). reset input sets port 0 to input mode. figure 6-1 shows a block diagram of port 0. figure 6-1. block di agram of p00 to p07 internal bus rd wr port wr pm output latch (p00 to p07) pm00 to pm07 p00 to p07 selector pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 6 port functions user?s manual u14826ej4v0ud 65 6.2.2 port 2 this is a 2-bit i/o port with output latches. port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (pm2). reset input sets port 2 to input mode. figures 6-2 and 6-3 show block diagrams of port 2. figure 6-2. block diagram of p20 p20/tmo /bsfo rd wr port wr pm output latch (p20) pm20 alternate function alternate function internal bus selector pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 6 port functions user?s manual u14826ej4v0ud 66 figure 6-3. block diagram of p21 p21/tmi rd wr port wr pm alternate function output latch (p21) pm21 internal bus selector pm: port mode register rd: port 2 read signal wr: port 2 write signal 6.2.3 port 4 this is a 4-bit input-only port. mask rom versions can specify an on-chip pull-up resi stor by means of the mask option. the port is also used as key return input. reset input sets port 4 to input mode. figure 6-4 shows a block diagram of port 4. figure 6-4. block di agram of p40 to p43 p40/kr10 to p43/kr13 rd alternate function v dd mask option resistor (mask rom versions only. eeprom versions have no pull-up resistor.) internal bus rd: port 4 read signal
chapter 6 port functions user?s manual u14826ej4v0ud 67 6.3 port function control registers the following registers are used to control the ports. port mode registers (pm0, pm2) (1) port mode registers (pm0, pm2) pm0 and pm2 are registers for which port i/o settings can be controlled in 1-bit units. each port mode register is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. when port pins are used for alternate functions, the corresponding port mode regist er and output latch must be set or reset as described in table 6-3. figure 6-5. format of port mode register pmmn 0 output mode (output buffer on) input mode (output buffer off) 1 pmn pin input/output mode selection (m = 0, 2, n = 0 to 7) pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pm0 76 54 symbol address after reset r/w ff20h ffh r/w 3210 1 1 1 1 1 1 pm21 pm20 pm2 ff22h ffh r/w table 6-3. port mode register and output latch settings for us ing alternate functions alternate function pin name name input/output pm p tmo output 0 0 p20 bsfo output 0 0 p21 tmi input 1 remark : don?t care pm : port mode register p : port output latch
chapter 6 port functions user?s manual u14826ej4v0ud 68 6.4 operation of port functions the operation of a port differs depending on whether the port is set to input or output mode, as described below. 6.4.1 writing to i/o port (1) in output mode a value can be written to the output la tch of a port by using a transfer inst ruction. the cont ents of the output latch can be output from the pins of the port. the data once written to t he output latch is retained until new dat a is written to the output latch. (2) in input mode a value can be written to the output latc h by using a transfer instruction. however, the status of the port pin is not changed because the out put buffer is off. the data once written to t he output latch is retained until new dat a is written to the output latch. caution a 1-bit memory manipulation instruction is executed to manipulate one bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of a port consisti ng both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined. 6.4.2 reading from i/o port (1) in output mode the contents of the out put latch can be read by using a transfer inst ruction. the content s of the output latch are not changed. (2) in input mode the status of a pin can be read by using a transfer instruction. the contents of the output latch are not changed. 6.4.3 arithmetic operation of i/o port (1) in output mode an arithmetic operation can be performed with the contents of the output latch. the re sult of the operation is written to the output latch. the contents of the out put latch are output from the port pins. the data once written to t he output latch is retained until new dat a is written to the output latch. (2) in input mode the contents of the output latch become undefined. however, the status of the pin is not changed because the output buffer is off. caution a 1-bit memory manipulation instruction is executed to manipulate one bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of a port consisti ng both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined.
user?s manual u14826ej4v0ud 69 chapter 7 clock generator ( pd789860 subseries) 7.1 clock generator functions the clock generator generates the clock to be s upplied to the cpu and peripheral hardware. the following type of system clock oscillator is used. ? system clock (crystal/ceramic) oscillator this circuit oscillates at 1.0 to 5.0 mhz. oscilla tion can be stopped by executi ng the stop instruction. 7.2 clock generator configuration the clock generator includes the following hardware. table 7-1. configuration of clock generator item configuration control register processor cl ock control register (pcc) oscillator crystal/ceramic oscillator figure 7-1. block diag ram of clock generator prescaler system clock oscillator f x prescaler standby controller wait controller cpu clock (f cpu ) stop f x 2 2 clock to peripheral hardware pcc0 internal bus processor clock control register (pcc) x1 x2 selector
chapter 7 clock generator ( pd789860 subseries) user?s manual u14826ej4v0ud 70 7.3 clock generator control register the clock generator is controll ed by the following register: ? processor clock control register (pcc) (1) processor clock control register (pcc) pcc selects the cpu clock and the division ratio. pcc is set with a 1-bit or 8-bit me mory manipulation instruction. reset input sets pcc to 02h. figure 7-2. format of processo r clock control register cpu clock (f cpu ) selection pcc0 0 1 f x f x /2 2 0 0 0 0 0 0 pcc0 0 pcc 76 54 symbol address after reset r/w fffbh 02h r/w 3210 minimum instruction execution time: 2/f cpu at f x = 5.0 mhz operation 0.4 s 1.6 s caution be sure to clear bits 0 and 2 to 7 to 0. remark f x : system clock oscillation frequency
chapter 7 clock generator ( pd789860 subseries) user?s manual u14826ej4v0ud 71 7.4 system clock oscillators 7.4.1 system clock oscillator the system clock oscillator is oscillat ed by the crystal or ceramic resonator (5.0 mhz typ.) connected across the x1 and x2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the x1 pin, and input the inverted signal to the x2 pin. figure 7-3 shows the external circui t of the system clock oscillator. figure 7-3. external circuit of system clock oscillator (a) crystal or ceramic osc illation (b) external clock v ss x1 x2 crystal or ceramic resonator external clock x1 x2 caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in figure 7-3 to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator.
chapter 7 clock generator ( pd789860 subseries) user?s manual u14826ej4v0ud 72 7.4.2 examples of incorr ect resonator connection figure 7-4 shows examples of incorrect resonator connections. figure 7-4. examples of incorr ect resonator connection (1/2) (a) wiring too long (b) crossed signal line v ss x1 x2 v ss x1 x2 portn (n = 0, 2, 4) (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 high current v ss x1 ab c portn (n = 0, 2, 4) v dd high current x2
chapter 7 clock generator ( pd789860 subseries) user?s manual u14826ej4v0ud 73 figure 7-4. examples of incorr ect resonator connection (2/2) (e) signal is fetched v ss x1 x2 7.4.3 frequency divider the frequency divider divides the system clock oscillator output (f x ) and generates clocks.
chapter 7 clock generator ( pd789860 subseries) user?s manual u14826ej4v0ud 74 7.5 clock generator operation the clock generator generates the following clocks and controls the operati on modes of the cpu, such as standby mode: ? system clock f x ? cpu clock f cpu ? clock to peripheral hardware the operation of the clock gener ator is determined by the processor clo ck control register (pcc) as follows: (a) the slow mode (1.6 s: at 5.0 mhz operation) of the system clock is select ed when the reset signal is generated (pcc = 02h). while a low level is input to the reset pin, oscillation of the system clock is stopped. (b) two types of minimum instruction execution time (f cpu ) (0.4 s, 1.6 s: at 5.0 mhz operation) can be selected by setting pcc. (c) two standby modes, stop and halt, can be used. (d) the clock for the peripheral hardw are is generated by dividing the frequency of the system clo ck. therefore, the peripheral hardware stops when the system clock stops (except for an external input clock).
chapter 7 clock generator ( pd789860 subseries) user?s manual u14826ej4v0ud 75 7.6 changing setting of cpu clock 7.6.1 time required fo r switching cpu clock the cpu clock can be selected by using bit 1 (pcc0) of the processor clock control register (pcc). actually, the specified clock is not selected immediately after the se tting of pcc has been changed, and the old clock is used for the duration of se veral instructions after that (see table 7-2 ). table 7-2. maximum time re quired for switching cpu clock set value before switching set value after switching pcc0 pcc0 pcc0 0 1 0 4 clocks 1 2 clocks remark two clocks are the minimum instruction execut ion time of the cpu clock before switching. 7.6.2 switching cpu clock the following figure illustrates how the cpu clock is switched. figure 7-5. switching between system clock and cpu clock cpu clock reset v dd slow operation fast operation wait (6.55 ms: @5.0 mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on pow er application. the effect of resetting is released when the reset pin is later made high, and the system clock starts oscillati ng. at this time, the oscillation stabilization time (2 15 /f x ) is automatically secured. after that, the cpu starts instruction execut ion at the slow speed of the system clock (1.6 s: @5.0 mhz operation). <2> after the time required for the v dd voltage to rise to the level at wh ich the cpu can operat e at the high speed has elapsed, the processor clock cont rol register (pcc) is rewritten so that the high-s peed operation can be selected.
user?s manual u14826ej4v0ud 76 chapter 8 clock generator ( pd789861 subseries) 8.1 clock generator functions the clock generator generates the clock to be s upplied to the cpu and peripheral hardware. the following type of system clock oscillator is used. ? system clock (rc) oscillator this circuit oscillates at 1.0 mhz 15%. oscillation can be stopped by ex ecuting the stop instruction. 8.2 clock generator configuration the clock generator includes the following hardware. table 8-1. configuration of clock generator item configuration control register processor cl ock control register (pcc) oscillator rc oscillator figure 8-1. block diag ram of clock generator prescaler system clock oscillator f cc prescaler standby controller wait controller cpu clock (f cpu ) stop f cc 2 2 clock to peripheral hardware pcc0 internal bus processor clock control register (pcc) cl1 cl2 selector
chapter 8 clock generator ( pd789861 subseries) user?s manual u14826ej4v0ud 77 8.3 clock generator control register the clock generator is controll ed by the following register: ? processor clock control register (pcc) (1) processor clock control register (pcc) pcc selects the cpu clock and the division ratio. pcc is set with a 1-bit or 8-bit me mory manipulation instruction. reset input sets pcc to 02h. figure 8-2. format of processo r clock control register cpu clock (f cpu ) selection pcc0 0 1 f cc f cc /2 2 0 0 0 0 0 0 pcc0 0 pcc 76 54 symbol address after reset r/w fffbh 02h r/w 3210 minimum instruction execution time: 2/f cpu at f cc = 1.0 mhz operation 2.0 s 8.0 s caution be sure to clear bits 0 and 2 to 7 to 0. remark f cc : system clock oscillation frequency
chapter 8 clock generator ( pd789861 subseries) user?s manual u14826ej4v0ud 78 8.4 system clock oscillators 8.4.1 system clock oscillator the system clock oscillator is oscillat ed by the resistor (r) and capacitor (c ) (1.0 mhz typ.) connected across the cl1 and cl2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the cl1 pin, and input the inverted signal to the cl2 pin. figure 8-3 shows the external circui t of the system clock oscillator. figure 8-3. external circuit of system clock oscillator (a) rc oscillation (b) external clock v ss cl1 r c cl2 external clock cl1 cl2 caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in figure 8-3 to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator.
chapter 8 clock generator ( pd789861 subseries) user?s manual u14826ej4v0ud 79 8.4.2 examples of incorr ect resonator connection figure 8-4 shows examples of incorrect resonator connections. figure 8-4. examples of incorr ect resonator connection (1/2) (a) wiring too long (b) crossed signal line v ss cl2 cl1 v ss cl2 portn (n = 0, 2, 4) cl1 (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss cl2 cl1 high current v ss v dd cl2 cl1 ab portn (n = 0, 2, 4) high current
chapter 8 clock generator ( pd789861 subseries) user?s manual u14826ej4v0ud 80 figure 8-4. examples of incorr ect resonator connection (2/2) (e) signal is fetched v ss cl2 cl1 8.4.3 frequency divider the frequency divider divides the system clock oscillator output (f cc ) and generates clocks.
chapter 8 clock generator ( pd789861 subseries) user?s manual u14826ej4v0ud 81 8.5 clock generator operation the clock generator generates the following clocks and controls the operati on modes of the cpu, such as standby mode: ? system clock f cc ? cpu clock f cpu ? clock to peripheral hardware the operation of the clock gener ator is determined by the processor clo ck control register (pcc) as follows: (a) the slow mode (8.0 s: at 1.0 mhz operation) of the system clock is select ed when the reset signal is generated (pcc = 02h). while a low level is input to the reset pin, oscillation of the system clock is stopped. (b) two types of minimum instruction execution time (f cpu ) (2.0 s, 8.0 s: at 1.0 mhz operation) can be selected by the pcc setting. (c) two standby modes, stop and halt, can be used. (d) the clock for the peripheral hardw are is generated by dividing the frequency of the system clo ck. therefore, the peripheral hardware stops when the system clock stops (except for an external input clock).
chapter 8 clock generator ( pd789861 subseries) user?s manual u14826ej4v0ud 82 8.6 changing setting of cpu clock 8.6.1 time required fo r switching cpu clock the cpu clock can be selected by using bit 1 (pcc0) of the processor clock control register (pcc). actually, the specified clock is not selected immediately after the se tting of pcc has been changed, and the old clock is used for the duration of se veral instructions after that (see table 8-2 ). table 8-2. maximum time re quired for switching cpu clock set value before switching set value after switching pcc0 pcc0 pcc0 0 1 0 4 clocks 1 2 clocks remark two clocks are the minimum instruction execut ion time of the cpu clock before switching. 8.6.2 switching cpu clock the following figure illustrates how the cpu clock is switched. figure 8-5. switching between system clock and cpu clock cpu clock reset v dd slow operation fast operation wait (128 s: @1.0 mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on pow er application. the effect of resetting is released when the reset pin is later made high, and the system clock starts oscillati ng. at this time, the oscillation stabilization time (2 7 /f cc ) is automatically secured. after that, the cpu starts instruction execut ion at the slow speed of the system clock (8.0 s: @1.0 mhz operation). <2> after the time required for the v dd voltage to rise to the level at wh ich the cpu can operat e at the high speed has elapsed, the processor clock cont rol register (pcc) is rewritten so that the high-s peed operation can be selected.
user?s manual u14826ej4v0ud 83 chapter 9 8-bit timers 30 and 40 9.1 8-bit timers 30, 40 functions the pd789860, 789861 subseries have on chip an 8-bit timer (timer 30) (1 channel) and an 8-bit timer/event counter (timer 40) (1 channel). t he operation modes shown in the table below are possible by means of mode register settings. table 9-1. mode list channel mode timer 30 timer 40 8-bit timer counter mode (discrete mode) 16-bit timer counter mode (cascade connection mode) carrier generator mode pwm output mode (1) 8-bit timer counter mode (discrete mode) the following functions can be used. 8-bit resolution interval timer 8-bit resolution external event counter (timer 40 only) 8-bit resolution square wave output (2) 16-bit timer counter m ode (cascade connection mode) operates as a 16-bit timer/event counter due to cascade connection. the following functions can be used. 16-bit resolution interval timer 16-bit resolution external event counter 16-bit resolution square wave output (3) carrier generator mode in this mode, the carrier clock generated by ti mer 40 is output in the cycle set by timer 30. (4) pwm output mode (timer 40 only) outputs a pulse of an arbitrary duty factor set by timer 40.
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 84 9.2 8-bit timers 30, 40 configuration the 8-bit timers include the following hardware. table 9-2. configuration of 8-bit timers 30, 40 item configuration timer counter 8 bits 2 (tm30, tm40) registers compare registers: 8 bits 3 (cr30, cr40, crh40) timer output 1 (tmo) control registers 8-bit timer mode control register 30 (tmc30) 8-bit timer mode control register 40 (tmc40) carrier generator output control register 40 (tca40) port mode register 2 (pm2) port 2 (p2)
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 85 figure 9-1. time r 30 block diagram tce30 tcl300 tcl301 8-bit timer mode control register 30 (tmc30) selector decoder 8-bit compare register 30 (cr30) 8-bit timer counter 30 (tm30) selector internal reset signal from figure 9-2 (e) timer 40 match signal (in cascade connection mode) to figure 9-2 (f) timer 30 match signal ( in cascade connection mode ) from figure 9-2 (d) count operation start signal (in cascade connection mode) inttm30 f clk /2 6 f clk /2 8 timer 40 interrupt request signal (from figure 9-2 (b)) carrier clock (from figure 9-2 (c)) clear cascade connection mode match internal bus ovf to figure 9-2 (g) timer 30 match signal (in carrier generator mode) bit 7 of tm40 (from figure 9-2 (a)) tmd300 tmd301 tcl302 (a) (b) (c) (d) (e) (f) (g) selector selector remark f clk : f x or f cc
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 86 figure 9-2. time r 40 block diagram tce40 tcl402 tcl401 tcl400 tmd401 tmd400 toe40 8-bit timer mode control register 40 (tmc40) decoder 8-bit timer counter 40 (tm40) f/f from figure 9-1 (f) tm30 match signal (in cascade connection mode) to figure 9-1 (d) count operation start signal to timer 30 (in cascade connection mode) to figure 9-1 (e) tm40 timer counter match signal (in cascade connection mode) clear 8-bit compare register 40 (cr40) selector output controller note rmc40 nrzb40 nrz40 carrier generator output control register 40 (tca40) count clock input signal to tm30 internal reset signal inttm40 bit 7 of tm40 (in cascade connection mode) to figure 9-1 (a) match tmo/p20/bsfo to figure 9-1 (c) carrier clock reset carrier generator mode pwm mode cascade connection mode 8-bit compare register h40 (crh40) internal bus ovf timer 40 interrupt request signal to figure 9-1 (b) timer counter match signal from timer 30 (in carrier generator mode) from figure 9-1 (g) f clk f clk /2 2 tmi/p21 tmi/2 tmi/2 2 tmi/2 3 (d) (e) (f) (b) (a) (c) (g) selector prescaler note for details, see figure 9-3 . remark f clk : f x or f cc
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 87 figure 9-3. block diagram of output controller (timer 40) f/f rmc40 nrz40 toe40 pm20 p20 output latch tmo/p20/ bsfo carrier generator mode carrier clock selector (1) 8-bit compare register 30 (cr30) this register is an 8-bit register that always compares the count value of 8-bit timer counter 30 (tm30) with the value set in cr30 and generates an interr upt request (inttm30) if they match. cr30 is set with an 8-bit memory manipulation instruction. reset input makes this register undefined. caution cr30 cannot be used in pwm output mode. (2) 8-bit compare register 40 (cr40) this register is an 8-bit register that always compares the count value of 8-bit timer counter 40 (tm40) with the value set in cr40 and generates an interrupt reques t (inttm40) if they match. in addition, when cascade-connected to tm30 and used as a 16-bit timer/ event counter, an interrupt request (inttm40) is generated only if tm30 matches with cr30 and tm40 ma tches with cr40 simultaneous ly (inttm30 is not generated). in carrier generator mode or pwm output mode, set the low-level width of the timer output. cr40 is set with an 8-bit memory manipulation instruction. reset input makes this register undefined. (3) 8-bit compare register h40 (crh40) in carrier generator mode or pwm out put mode, writing a crh40 value sets the width of high level timer output. the value set in crh40 is const antly compared with the tm40 count value, and an interrupt request (inttm40) is generated if they match. crh40 is set with an 8-bit memory manipulation instruction. reset input makes this register undefined. (4) 8-bit timer counters 30 and 40 (tm30, tm40) these 8-bit registers count pulse counts. each of tm30 and tm40 is read with an 8-bi t memory manipulation instruction. reset input clears these registers to 00h. the conditions under which tm30 and tm40 are cleared to 00h are shown next.
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 88 (a) discrete mode (i) tm30 reset clearing of tce30 (bit 7 of 8-bit time r mode control register 30 (tmc30)) to 0 match of tm30 and cr30 tm30 count value overflow (ii) tm40 reset clearing of tce40 (bit 7 of 8-bit time r mode control register 40 (tmc40)) to 0 match of tm40 and cr40 tm40 count value overflow (b) cascade connection mode (tm30, tm 40 simultaneously cleared to 00h) reset clearing of the tce40 flag to 0 simultaneous match of tm 30 with cr30 and tm40 with cr40 tm30 and tm40 count values overflow simultaneously (c) carrier generator/pwm output mode (tm40 only) reset clearing of the tce40 flag to 0 match of tm40 and cr40 match of tm40 and crh40 tm40 count value overflow 9.3 8-bit timers 30, 40 control registers the 8-bit timers are controlled by the following five registers. 8-bit timer mode control register 30 (tmc30) 8-bit timer mode control register 40 (tmc40) carrier generator output c ontrol register 40 (tca40) port mode register 2 (pm2) port 2 (p2)
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 89 (1) 8-bit timer mode control register 30 (tmc30) tmc30 is the register that contro ls the setting of the timer 30 count clock and the setting of the operating mode. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 9-4. format of 8-bit timer mode control register 30 symbol <7> 6 5 4 3 2 1 0 address after reset r/w tmc30 tce30 0 tcl302 tcl301 tcl300 tmd301 tmd300 0 ff52h 00h r/w tce30 tm30 count operation control note 1 0 clears tm30 count value and halt operation 1 starts count operation selection of timer 30 count clock tcl302 tcl301 tcl300 when operating at f x = 5.0 mhz when operating at f cc = 1.0 mhz 0 0 0 f x /2 6 (78.1 khz) f cc /2 6 (15.6 khz) 0 0 1 f x /2 8 (19.5 khz) f cc /2 8 (3.91 khz) 0 1 0 timer 40 match signal 0 1 1 carrier clock generated by timer 40 other than above setting prohibited tmd301 tmd300 tmd401 tmd400 selection of timer 30, timer 40 operating mode note 2 0 0 0 0 discrete mode 0 1 0 1 cascade connection mode 0 0 1 1 carrier generator mode 0 0 1 0 pwm output mode other than above setting prohibited notes 1. in cascade connection mode, since count operations are controlled by tce40 (bit 7 of tmc40), tce30 is ignored even if it is set. 2. the selection of operating m ode is made by combining the tw o registers tmc30 and tmc40. cautions 1. be sure to clear bits 0 and 6 to 0. 2. in cascade connection mode, timer 40 output si gnal is forcibly selected for count clock. remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : system clock oscillation frequency (rc oscillation)
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 90 (2) 8-bit timer mode control register 40 (tmc40) tmc40 is the register that contro ls the setting of the timer 40 count clock and the setting of the operating mode. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 9-5. format of 8-bit timer mode control register 40 symbol <7> 6 5 4 3 2 1 <0> address after reset r/w tmc40 tce40 0 tcl402 tcl401 tcl400 tmd401 tmd400 toe40 ff56h 00h r/w tce40 tm40 count operation control note 1 0 clears tm40 count value and halt operation (in cascade connection mode, the tm30 count value is simultaneously cleared as well.) 1 starts count operation (in casc ade connection mode, the tm30 count operat ion is simultaneously started as well.) selection of timer 40 count clock tcl402 tcl401 tcl400 when operating at f x = 5.0 mhz when operating at f cc = 1.0 mhz 0 0 0 f x (5.0 mhz) f cc (1.0 mhz) 0 0 1 f x /2 2 (1.25 mhz) f cc /2 2 (250 khz) 0 1 0 f tmi 0 1 1 f tmi /2 1 0 0 f tmi /2 2 1 0 1 f tmi /2 3 tmd301 tmd300 tmd401 tmd400 selection of timer 30, timer 40 operating mode note 2 0 0 0 0 discrete mode 0 1 0 1 cascade connection mode 0 0 1 1 carrier generator mode 0 0 1 0 pwm output mode other than above setting prohibited toe40 timer output control 0 output disabled 1 output enabled (port mode) notes 1. in cascade connection mode, since count operations are controlled by tce40, tce30 (bit 7 of tmc30) is ignored even if it is set. 2. the selection of operating m ode is made by combining the tw o registers tmc30 and tmc40. caution be sure to clear bit 6 to 0. remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : system clock oscillation frequency (rc oscillation) 3. f tmi : external clock input from tmi/p21 pin
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 91 (3) carrier generator output control register 40 (tca40) tca40 is used to set the timer output data in the carrier generator mode. this register is set with an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 9-6. format of carrier gene rator output control register 40 symbol 7 6 5 4 3 2 1 0 address after reset r/w tca40 0 0 0 0 0 rmc40 nrzb40 nrz40 ff57h 00h w rmc40 remote controller output control 0 when nrz40 = 1, a carrier pulse is output to the tmo/p20/bsfo pin 1 when nrz40 = 1, a high level is output to the tmo/p20/bsfo pin nrzb40 this bit stores the data that nrz40 will output next. data is transferred to nrz40 upon the generation of a timer 30 match signal. input the necessary value in nrzb40 in advance by program. nrz40 no return zero data 0 a low level is output (the carrier clock is stopped) 1 a carrier pulse or high level is output cautions 1. be sure to clear bits 3 to 7 to 0. 2. tca40 cannot be set with a 1-bit memory mani pulation instruction. be sure to use an 8- bit memory manipulation in struction to set tca40. 3. the nrz40 flag can be written only when carrier generator output is stopped (toe40 = 0). the data cannot be o verwritten when toe40 = 1. 4. when the carrier generator is stopped once and then started again, nrzb40 does not hold the previous data. re-set data to nrzb40. at this time, a 1-bit memory manipulation instruction must not be used . be sure to use an 8-bit memory manipulation instruction. 5. to enable operation in the carrier generator mode, set a val ue to the compare registers (cr30, cr40, and crh40), and input the n ecessary value to the nrz b40 and nrz40 flags in advance. otherwise, the signal of the timer match ci rcuit will become unstable and the nrz40 flag will be undefined. 6. note that the pd78e9860 and 78e9861 have the following restrictions (which do not apply to the mask rom version and the pd78e9860a and 78e9861a). (a) while inttm30 (interrupt ge nerated by the match signal of timer 30) is being output, accessing tca40 is prohibited. (b) accessing tca40 is prohibited while 8- bit timer/counter 30 (tm30) is 00h. to access tca40 while tm30 = 00h, wait for more than half a period of the tm30 count clock and then rewrite tca40.
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 92 (4) port mode register 2 (pm2) pm2 sets port 2 to input/output in 1-bit units. when using the p20/tmo/bsfo pin as a timer out put, clear the pm20 and p20 output latch to 0. when using the p21/tmi pin as a timer input, set the pm21 to 1. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 9-7. format of port mode register 2 symbol 7 6 5 4 3 2 1 0 address after reset r/w pm2 1 1 1 1 1 1 pm21 pm20 ff22h ffh r/w pm2m p2m pin input/output mode (m = 0, 1) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 93 9.4 8-bit timers 30, 40 operation 9.4.1 operation as 8-bit timer counter timer 30 and timer 40 can independently be used as an 8-bit timer counter. the following modes can be used for the 8-bit timer counter. ? interval timer with 8-bit resolution ? external event counter with 8- bit resolution (timer 40 only) ? square wave output with 8-bi t resolution (timer 40 only) (1) operation as interval timer with 8-bit resolution the interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register n0 (crn0). to operate 8-bit timer n0 as an interval timer, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter n0 (tmn0) (tcen0 = 0). <2> disable timer output of tmo (toe40 = 0) note . <3> set a count value in crn0. <4> set the operation mode of timer n0 to 8-bit timer counter mode (see figures 9-4 and 9-5 ). <5> set the count clock for timer n0 (see tables 9-3 to 9-6 ). <6> enable the operation of tmn0 (tcen0 = 1). when the count value of 8-bit timer counter n0 (tmn0) matches the value set in crn0, tmn0 is cleared to 0 and continues counting. at the same time, an interrupt request signal (inttmn0) is generated. tables 9-3 to 9-6 show interval time, and figures 9-8 to 9-13 show the timing of t he interval timer operation. note timer 40 only caution be sure to stop the timer operation before overwriting the count cl ock with different data. remark n = 3, 4
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 94 table 9-3. interval time of timer 30 (during f x = 5.0 mhz operation) tcl302 tcl301 tcl300 minimum interval time maximum interval time resolution 0 0 0 2 6 /f x (12.8 s) 2 14 /f x (3.28 ms) 2 6 /f x (12.8 s) 0 0 1 2 8 /f x (51.2 s) 2 16 /f x (13.1 ms) 2 8 /f x (51.2 s) 0 1 0 input cycle of timer 40 match signal input cycle of timer 40 match signal 2 8 input cycle of timer 40 match signal 0 1 1 carrier clock cycle generated by timer 40 carrier clock cycle generated by timer 40 2 8 carrier clock cycle generated by timer 40 remark f x : system clock oscillation frequency (ceramic/crystal oscillation) table 9-4. interval time of timer 30 (during f cc = 1.0 mhz operation) tcl302 tcl301 tcl300 minimum interval time maximum interval time resolution 0 0 0 2 6 /f cc (64 s) 2 14 /f cc (16.4 ms) 2 6 /f cc (64 s) 0 0 1 2 8 /f cc (256 s) 2 16 /f cc (65.5 ms) 2 8 /f cc (256 s) 0 1 0 input cycle of timer 40 match signal input cycle of timer 40 match signal 2 8 input cycle of timer 40 match signal 0 1 1 carrier clock cycle generated by timer 40 carrier clock cycle generated by timer 40 2 8 carrier clock cycle generated by timer 40 remark f cc : system clock oscillation frequency (rc oscillation) table 9-5. interval time of timer 40 (during f x = 5.0 mhz operation) tcl402 tcl401 tcl400 minimum interval time maximum interval time resolution 0 0 0 1/f x (0.2 s) 2 8 /f x (51.2 s) 1/f x (0.2 s) 0 0 1 2 2 /f x (0.8 s) 2 10 /f x (204.8 s) 2 2 /f x (0.8 s) 0 1 0 f tmi input cycle f tmi input cycle 2 8 f tmi input cycle 0 1 1 f tmi /2 input cycle f tmi /2 input cycle 2 8 f tmi /2 input cycle 1 0 0 f tmi /2 2 input cycle f tmi /2 2 input cycle 2 8 f tmi /2 2 input cycle 1 0 1 f tmi /2 3 input cycle f tmi /2 3 input cycle 2 8 f tmi /2 3 input cycle remark f x : system clock oscillation frequency (ceramic/crystal oscillation) table 9-6. interval time of timer 40 (during f cc = 1.0 mhz operation) tcl402 tcl401 tcl400 minimum interval time maximum interval time resolution 0 0 0 1/f cc (1.0 s) 2 8 /f cc (256 s) 1/f cc (1.0 s) 0 0 1 2 2 /f cc (4.0 s) 2 10 /f cc (1024 s) 2 2 /f cc (4.0 s) 0 1 0 f tmi input cycle f tmi input cycle 2 8 f tmi input cycle 0 1 1 f tm i/2 input cycle f tmi /2 input cycle 2 8 f tmi /2 input cycle 1 0 0 f tmi /2 2 input cycle f tmi /2 2 input cycle 2 8 f tmi /2 2 input cycle 1 0 1 f tmi /2 3 input cycle f tmi /2 3 input cycle 2 8 f tmi /2 3 input cycle remark f cc : system clock oscillation frequency (rc oscillation)
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 95 figure 9-8. timing of interval timer oper ation with 8-bit resolution (basic operation) count stop count clock crn0 tcen0 inttmn0 tmo note n t tmn0 n 00h 01h n 00h 01h n 00h 00h 01h 00h 01h clear clear clear count start interrupt acknowledgement interrupt acknowledgement interrupt acknowledgement interval time interval time note timer 40 only remarks 1. interval time: (n + 1) t: n = 00h to ffh 2. n = 3, 4 figure 9-9. timing of interval timer operation with 8-bit resolution (when crn0 is cleared to 00h) count clock crn0 tcen0 inttmn0 tmo note 00h tmn0 00h count start note timer 40 only remark n = 3, 4
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 96 figure 9-10. timing of interval timer operati on with 8-bit resolution (when crn0 is set to ffh) count clock crn0 tcen0 inttmn0 tmo note ffh tmn0 ffh 00h 01h 00h 01h 00h ffh 00h 01h ffh ffh 00h clear clear clear count start note timer 40 only remark n = 3, 4 figure 9-11. timing of interval ti mer operation with 8-bit resolution (when crn0 changes from n to m (n < m)) count clock crn0 tcen0 inttmn0 tmo note tmn0 n 00h 00h n 00h 01h 00h 01h m nm n m clear clear clear count start interrupt acknowledgement interrupt acknowledgement crn0 overwritten note timer 40 only remark n = 3, 4
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 97 figure 9-12. timing of interval ti mer operation with 8-bit resolution (when crn0 changes from n to m (n > m)) count clock crn0 tcen0 inttmn0 tmo note tmn0 00h 00h 00h n ? 1 n mn m n m 00h ffh m h clear clear clear tmn0 overflows because m < n crn0 overwritten note timer 40 only remark n = 3, 4
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 98 figure 9-13. timing of interval ti mer operation with 8-bit resolution (when timer 40 match signal is sel ected for timer 30 count clock) timer 40 count clock cr40 tce40 inttm40 tmo tm40 n 00h m 00h 00h 01h m n m 00h m 00h 00h 01h y ? 1 y 00h y 00h y input clock to timer 30 (timer 40 match signal) inttm30 tce30 cr30 tm30 clear clear clear clear count start count start remark n = 3, 4
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 99 (2) operation as external event counter with 8-bit resolution (timer 40 only) the external event counter counts the number of external clock pulses input to the tmi/p21 pin by using 8-bit timer counter 40 (tm40). to operate timer 40 as an external event counter , settings must be made in the following sequence. <1> disable operation of 8-bit time r counter 40 (tm40) (tce40 = 0). <2> disable timer output of tmo (toe40 = 0). <3> set p21 to input mode (pm21 = 1). <4> select the external input clock for timer 40 (see tables 9-5 and 9-6 ). <5> set the operation mode of timer 40 to 8-bit timer counter mode (see figures 9-4 and 9-5 ). <6> set a count value in cr40. <7> enable the operati on of tm40 (tce40 = 1). each time the valid edge is input, the value of tm40 is incremented. when the count value of tm40 matc hes the value set in cr40, tm40 is cleared to 00h and continues counting. at the same time, an interr upt request signal (inttm40) is generated. figure 9-14 shows the timing of the external event counter operation. caution be sure to stop the timer operation before overwriting the count cl ock with different data. figure 9-14. timing of operation of exte rnal event counter with 8-bit resolution tmi pin input tm40 count value cr40 tce40 inttm40 00h 01h 02h 03h 04h 05h n ? 1 n 00h 01h 02h 03h n remark n = 00h to ffh
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 100 (3) operation as square-wave output wit 8-bit resolution (timer 40 only) square waves of any frequency can be output at an interval specified by t he value preset in 8-bit compare register 40 (cr40). to operate timer 40 for square-wave output, se ttings must be made in the following sequence. <1> set p20 to output mode (pm20 = 0). <2> clear the output latches of p20 to 0. <3> disable operation of 8-bit time r counter 40 (tm40) (tce40 = 0). <4> set a count clock for timer 40 and enable output of tmo (toe40 = 1). <5> set a count value in cr40. <6> enable the operation of tm40 (tce40 = 1). when the count value of tm40 matches the value set in cr40, the tmo pin output will be inverted. through application of this mechanism, square waves of any frequency can be output. as soon as a match occurs, tm40 is cleared to 00h and continues counting. at the same time, an in terrupt request signal (inttm40) is generated. the square-wave output is cleared to 0 by setting tce40 to 0. tables 9-7 and 9-8 show the squar e-wave output range, and figure 9-15 shows the timing of square-wave output. caution be sure to stop the timer operation before overwriting the count cl ock with different data. table 9-7. square-wave output range of timer 40 (during f x = 5.0 mhz operation) tcl402 tcl401 tcl400 minimum pulse width maximum pulse width resolution 0 0 0 1/f x (0.2 s) 2 8 /f x (51.2 s) 1/f x (0.2 s) 0 0 1 2 2 /f x (0.8 s) 2 10 /f x (204.8 s) 2 2 /f x (0.8 s) remark f x : system clock oscillation frequency (ceramic/crystal oscillation) table 9-8. square-wave output range of timer 40 (during f cc = 1.0 mhz operation) tcl402 tcl401 tcl400 minimum pulse width maximum pulse width resolution 0 0 0 1/f cc (1.0 s) 2 8 /f cc (256 s) 1/f cc (1.0 s) 0 0 1 2 2 /f cc (4.0 s) 2 10 /f cc (1024 s) 2 2 /f cc (4.0 s) remark f cc : system clock oscillation frequency (rc oscillation)
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 101 figure 9-15. timing of square-wave output with 8-bit resolution interrupt acknowledgement interrupt acknowledgement count start count clock cr40 tce40 inttm40 tmo note n tm40 n 00h 01h n 00h 01h n 00h 01h 00h 01h t interrupt acknowledgement square-wave output cycle clear clear clear note the initial value of tmo is low level when output is enabled (toe40 = 1). remark square-wave output cycle = 2 (n+1) t: n = 00h to ffh
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 102 9.4.2 operation as 16-bit timer counter timer 30 and timer 40 can be used as a 16-bit timer counter using cascade connection. in this case, 8-bit timer counter 30 (tm30) is the higher 8 bits and 8-bit timer counter 40 (tm40) is the lower 8 bits. 8-bit timer 40 controls reset and clear. the following modes can be used for the 16-bit timer counter. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square wave output with 16-bit resolution (1) operation as interval timer with 16-bit resolution the interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register 30 (cr30) and 8-bit compare register 40 (cr40). to operate as an interval timer with 16-bit resoluti on, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter 30 (tm 30) and 8-bit timer counter 40 (tm40) (tce30 = 0, tce40 = 0). <2> disable timer output of tmo (toe40 = 0) note 1 . <3> set the count clock for timer 40 (see tables 9-9 and 9-10 ). <4> set the operation mode of timer 30 and ti mer 40 to 16-bit timer counter mode (see figures 9-4 and 9- 5 ). <5> set a count value in cr30 and cr40. <6> enable the operation of tm30 and tm40 (tce40 = 1 note 2 ). notes 1. timer 40 only 2. start and clear of the timer in the 16-bit time r counter mode are contro lled by tce40 (the value of tce30 is invalid). when the count values of tm30 and tm40 match the values set in cr30 and cr40 respectively, both tm30 and tm40 are simultaneously cleared to 00h and counting c ontinues. at the same time, an interrupt request signal (inttm40) is generated (inttm30 is not generated). tables 9-9 and 9-10 show interval time, and figure 9-16 shows the timing of the interval timer operation. caution be sure to stop the timer operation before overwriting the count cl ock with different data.
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 103 table 9-9. interval time with 16-bit resolution (during f x = 5.0 mhz operation) tcl402 tcl401 tcl400 minimum interval time maximum interval time resolution 0 0 0 1/f x (0.2 s) 2 16 /f x (13.1 ms) 1/f x (0.2 s) 0 0 1 2 2 /f x (0.8 s) 2 18 /f x (52.4 ms) 2 2 /f x (0.8 s) 0 1 0 f tmi input cycle f tmi input cycle 2 16 f tmi input cycle 0 1 1 f tmi /2 input cycle f tmi /2 input cycle 2 16 f tmi /2 input cycle 1 0 0 f tmi /2 2 input cycle f tmi /2 2 input cycle 2 16 f tmi /2 2 input cycle 1 0 1 f tmi /2 3 input cycle f tmi /2 3 input cycle 2 16 f tmi /2 3 input cycle remark f x : system clock oscillation frequency (ceramic/crystal oscillation) table 9-10. interval time with 16-bit resolution (during f cc = 1.0 mhz operation) tcl402 tcl401 tcl400 minimum interval time maximum interval time resolution 0 0 0 1/f cc (1.0 s) 2 16 /f cc (65.5 ms) 1/f cc (1.0 s) 0 0 1 2 2 /f cc (4.0 s) 2 18 /f cc (262.1 ms) 2 2 /f cc (4.0 s) 0 1 0 f tmi input cycle f tmi input cycle 2 16 f tmi input cycle 0 1 1 f tmi /2 input cycle f tmi /2 input cycle 2 16 f tmi /2 input cycle 1 0 0 f tmi /2 2 input cycle f tmi /2 2 input cycle 2 16 f tmi /2 2 input cycle 1 0 1 f tmi /2 3 input cycle f tmi /2 3 input cycle 2 16 f tmi /2 3 input cycle remark f cc : system clock oscillation frequency (rc oscillation)
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 104 figure 9-16. timing of interval ti mer operation with 16-bit resolution interval time tm40 count clock tm40 count value cr40 tce40 inttm40 tmo ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm30 count clock tm30 00h x x ? 1 01h cr30 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h t not cleared because tm30 does not match cleared because tm30 and tm40 match simultaneously count start interrupt not generated because tm30 does not match interrupt acknowledgement interrupt acknowledgement remark interval time: (256x + n + 1) t: x = 00h to ffh, n = 00h to ffh
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 105 (2) operation as external event counter with 16-bit resolution the external event counter counts t he number of external clock pulses input to the tmi/p21 pin by tm30 and tm40. to operate as an external event c ounter with 16-bit resolution, setti ngs must be made in the following sequence. <1> disable operation of tm30 and tm40 (tce30 = 0, tce40 = 0). <2> disable timer output of tmo (toe40 = 0) note 1 . <3> set p21 to input mode (pm21 = 1). <4> select the external input clock for timer 40 (see tables 9-9 and 9-10 ). <5> set the operation mode of timer 30 and ti mer 40 to 16-bit timer counter mode (see figures 9-4 and 9- 5 ). <6> set a count value in cr30 and cr40. <7> enable the operation of tm30 and tm40 (tce40 = 1 note 2 ). notes 1. timer 40 only 2. start and clear of the timer in the 16-bit timer counter mode are controll ed by tce40 (the value of tce30 is invalid). each time the valid edge is input, the values of tm30 and tm40 are incremented. when the count values of tm30 and tm40 match the values set in cr30 and cr40 respectively, both tm30 and tm40 are simultaneously cleared to 00h and counting c ontinues. at the same time, an interrupt request signal (inttm40) is generated (inttm30 is not generated). figure 9-17 shows the timing of the external event counter operation. caution be sure to stop the timer operation before overwriting the count cl ock with different data.
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 106 figure 9-17. timing of external event counter operation with 16-bit resolution tmi pin input tm40 count value cr40 tce40 inttm40 ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm30 count clock tm30 00h x 01h cr30 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h x ? 1 not cleared because tm30 does not match cleared because tm30 and tm40 match simultaneously count start interrupt not generated because tm30 does not match interrupt acknowledgement interrupt acknowledgement x x remark x = 00h to ffh, n = 00h to ffh
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 107 (3) operation as square-wave output with 16-bit resolution square waves of any frequency can be out put at an interval specified by the count value preset in cr30 and cr40. to operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1> disable operation of tm30 and tm40 (tce30 = 0, tce40 = 0). <2> disable output of tmo (toe40 = 0). <3> set a count clock for timer 40. <4> clear p20 to output mode (pm20 = 0) and p20 output latch to 0 and enable tmo output (toe40 = 1). <5> set count values in cr30 and cr40. <6> enable the operati on of tm40 (tce40 = 1 note ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce40 (the value of tce30 is invalid). when the count values of tm30 and tm40 simult aneously match the values set in cr30 and cr40 respectively, the tmo pin output will be inverted. th rough application of this me chanism, square waves of any frequency can be output. as soon as a match o ccurs, tm30 and tm40 are cleared to 00h and counting continues. at the same time, an interrupt request si gnal (inttm40) is generated (inttm30 is not generated). the square-wave output is cleared to 0 by setting tce40 to 0. tables 9-11 and 9-12 show the squar e wave output range, and figure 9- 18 shows timing of square wave output. caution be sure to stop the timer operation before overwriting the count cl ock with different data. table 9-11. square-wave output ra nge with 16-bit resolution (during f x = 5.0 mhz operation) tcl402 tcl401 tcl400 minimum pulse time maximum pulse time resolution 0 0 0 1/f x (0.2 s) 2 16 /f x (13.1 ms) 1/f x (0.2 s) 0 0 1 2 2 /f x (0.8 s) 2 18 /f x (52.4 ms) 2 2 /f x (0.8 s) remark f x : system clock oscillation frequency (ceramic/crystal oscillation) table 9-12. square-wave output ra nge with 16-bit resolution (during f cc = 1.0 mhz operation) tcl402 tcl401 tcl400 minimum pulse time maximum pulse time resolution 0 0 0 1/f cc (1.0 s) 2 16 /f cc (65.5 ms) 1/f cc (1.0 s) 0 0 1 2 2 /f cc (4.0 s) 2 18 /f cc (262.1 ms) 2 2 /f cc (4.0 s) remark f cc : system clock oscillation frequency (rc oscillation)
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 108 figure 9-18. timing of square-wave output with 16-bit resolution tm40 count clock tm40 count value cr40 tce40 inttm40 tmo note ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm30 count clock tm30 00h x x ? 1 01h cr30 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h not cleared because tm30 does not match cleared because tm30 and tm40 match simultaneously count start interrupt not generated because tm30 does not match interrupt acknowledgement interrupt acknowledgement note the initial value of tmo is low level when output is enabled (toe40 = 1). remark x = 00h to ffh, n = 00h to ffh
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 109 9.4.3 operation as carrier generator an arbitrary carrier clock generated by tm 40 can be output in the cycle set in tm30. to operate timer 30 and timer 40 as carrier generator s, setting must be made in the following sequence. <1> disable operation of tm30 and tm40 (tce30 = 0, tce40 = 0). <2> disable timer output of tmo (toe40 = 0). <3> set count values in cr30, cr40, and crh40. <4> set the operation mode of time r 40 to carrier generator mode (see figures 9-4 and 9-5 ). <5> set the count clock for timer 30 and timer 40. <6> set remote control output to carrier pulse (rmc40 (bit 2 of carrier generator output control register 40 (tca40)) = 0). input the required value to nrzb 40 (bit 1 of tca40) by program. input a value to nrz40 (bit 0 of tca 40) before it is reloaded from nrzb40. <7> clear p20 to output mode (pm 20 = 0) and the p20 output latch to 0 and enable tmo output by setting toe40 to 1. <8> enable the operation of tm30 and tm40 (tce30 = 1, tce40 = 1). <9> save the value of nrzb40 to a general-purpose register. <10> when inttm30 rises, the value of nrzb40 is transfe rred to nrz40. after that, rewrite tca40 with an 8-bit memory manipulation instruction. input the value to be transferred to nrz40 next time to nrzb40, and input the value saved in <9> to nrz40. <11> generate the desired carrier signal by repeating <9> and <10>.
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 110 the operation of the carrier generator is as follows. <1> when the count value of tm40 ma tches the value set in cr40, an in terrupt request signal (inttm40) is generated and output of timer 40 is in verted, which makes the compare register switch from cr40 to crh40. <2> after that, when the count value of tm40 matches the value set in crh40, an interrupt request signal (inttm40) is generated and output of ti mer 40 is inverted again, which make s the compare register switch from crh40 to cr40. <3> the carrier clock is generated by repeating <1> and <2> above. <4> when the count value of tm30 ma tches the value set in cr30, an in terrupt request signal (inttm30) is generated. the rising edge of inttm30 is the data reload signal of nrz b40 and is transferred to nrz40. <5> when nrz40 is 1, a carrier clock is output from tmo pin. cautions 1. tca40 cannot be set with a 1-bit memory ma nipulation instruction. be sure to use an 8-bit memory manipulation instruction to set tca40. 2. the nrz40 flag can be wri tten only when carrier generator output is stopped (toe40 = 0). the data cannot be overwr itten when toe40 = 1. 3. when the carrier generator is stopped on ce and then started again, nrzb40 does not hold the previous data. re-set data to nrzb40. at this time, a 1-bit memory manipulation instruction must not be used. be sure to use an 8-bit memory ma nipulation instruction. 4. to enable operation in the carrier generator mode, set a val ue to the compare registers (cr30, cr40, and crh40), and input the necessar y value to the nrzb 40 and nrz40 flags in advance. otherwise, the signa l of the timer match circui t will become unstable and the nrz40 flag will be undefined. 5. note that the pd78e9860 and 78e9861 have the following rest rictions (which do not apply to the mask rom version and the pd78e9860a and 78e9861a). (a) while inttm30 (interrupt ge nerated by the match signal of timer 30) is being output, accessing tca40 is prohibited. (b) accessing tca40 is prohibited while 8- bit timer/counter 30 (tm30) is 00h. to access tca40 while tm30 = 00h, wait for more than half a period of the tm30 count clock and then rewrite tca40.
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 111 figure 9-19. timing of carrier generato r operation (when cr40 = n, crh40 = m (m > n)) tm40 count clock tm40 count value cr40 tce40 inttm40 m 00h n 00h 01h n crh40 m n 00h carrier clock n 00h 00h n m 00h 01h x 00h 01h x 00h 01h x 00h x 00h 01h tm30 cr30 tce30 inttm30 tm30 count clock 0 1 0 10 0 1 01 0 nrzb40 nrz40 tmo carrier clock clear clear clear clear count start x
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 112 figure 9-20. timing of carrier generato r operation (when cr40 = n, crh40 = m (m < n)) tm40 count clock tm40 count value cr40 tce40 inttm40 n 00h n crh40 m carrier clock n 00h 00h 01h x 00h 01h x 00h 01h x 00h x 00h 01h tm30 cr30 tce30 inttm30 tm30 count clock 0 1 0 10 0 1 01 0 nrzb40 nrz40 tmo carrier clock m 00h m m 00h m 00h clear clear clear clear count start x remark this timing chart shows an example in which the value of nrz40 is changed while the carrier clock is high.
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 113 figure 9-21. timing of carrier genera tor operation (when cr40 = crh40 = n) count clock tm40 count value cr40 tce40 inttm40 n 00h 00h 00h n crh40 n n carrier clock 00h 00h n n 00h 01h x 00h 01h x 00h 01h x 00h x 00h 01h tm30 cr30 tce30 inttm30 count pulse 0 1 0 10 0 1 01 0 nrzb40 nrz40 tmo carrier clock n n 00h clear clear clear clear clear count start x
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 114 9.4.4 operation as pwm output (timer 40 only) in the pwm output mode, a pulse of any duty ratio can be output by setting a low-level width using cr40 and a high-level width using crh40. to operate timer 40 in pwm output mode, setti ngs must be made in the following sequence. <1> disable operation of tm40 (tce40 = 0). <2> disable timer output of tmo (toe40 = 0). <3> set count values in cr40 and crh40. <4> set the operation mode of ti mer 40 to pwm output mode (see figure 9-5 ). <5> set the count clock for timer 40. <6> clear p20 to output mode (pm20 = 0) and the p20 output latch to 0 and enable timer output of tmo (toe40 = 1). <7> enable the operation of tm40 (tce40 = 1). the operation in the pwm out put mode is as follows. <1> when the count value of tm40 ma tches the value set in cr40, an in terrupt request signal (inttm40) is generated and output of timer 40 is in verted, which makes the compare register switch from cr40 to crh40. <2> a match between tm40 and cr40 clears the tm40 value to 00h and then counting starts again. <3> after that, when the count value of tm40 matches the value set in crh40, an interrupt request signal (inttm40) is generated and output of ti mer 40 is inverted again, which make s the compare register switch from crh40 to cr40. <4> a match between tm40 and crh40 clears the tm40 va lue to 00h and then counting starts again. a pulse of any duty ratio is output by repeating <1> to <4> above. fi gures 9-22 and 9-23 s how the operation timing in the pwm output mode.
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 115 figure 9-22. pwm output mode timing (basic operation) tm40 count clock tm40 count value cr40 tce40 inttm40 00h n 00h 01h n crh40 m n tmo note 00h 00h 01h m 01h 01h m 00h clear clear clear clear count start note the initial value of tmo is low level when output is enabled (toe40 = 1). figure 9-23. pwm output mode timing (when cr40 and crh40 are overwritten) tm40 count clock tm40 count value cr40 tce40 inttm40 00h n 00h 01h n crh40 m n tmo note m x y 00h 00h x 00h x ym clear clear clear clear count start 01h 00h note the initial value of tmo is low level when output is enabled (toe40 = 1).
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 116 9.5 notes on using 8-bit timers 30, 40 (1) error on starting timer an error of up to 1.5 clocks is included in the time between the timer being started and a match signal being generated. this is because the rising edge is detected and the count er is incremented if the timer is started while the count clock is high (see figure 9-24 ). figure 9-24. case of error o ccurrence of up to 1.5 clocks 8-bit timer counter n0 (tmn0) count pulse clear signal selected clock tcen0 delay a delay b selected clock tcen0 clear signal count pulse tmn0 counter value 00h 01h 02h 03h delay a delay b an error of up to 1.5 clocks occurs if the timer is started when the selected clock is high and delay a > delay b. remark n = 3, 4
chapter 9 8-bit timers 30 and 40 user?s manual u14826ej4v0ud 117 (2) count value if external clo ck input from tmi pin is selected when the external clock signal input from the tmi pin is selected as the count cl ock, the count value may start from 01h if the timer is enabled (tce40 = 0 1) while the tmi pin is high. this is because the input signal of the tmi pin is interna lly anded with the tce40 signal. c onsequently, the counter is incremented because the rising edge of the count cl ock is input to the timer immediately when the tce40 pin is set. depending on the delay timing, the count value is incr emented by one if the risi ng edge is input after the counter is cleared. counting is not affected if the rising edge is input before the counter is cleared (the counter operates normally). use the timer being aware that it has an error of one count, or take either of the following actions a or b. always start the timer when the tmi pin is low. save the count value to a control register when the timer is started, sub the c ount value with the count value saved to the contro l register when reading the count value, and take the result of sub as the true count value. figure 9-25. counting operation if timer is started when tmi is high tce40 flag tmi h rising edge detector counter clear increment (3) setting of 8-bit compare register n0 8-bit compare register n0 (crn0) can be cleared to 00h. therefore, one pulse can be c ounted when the 8-bit timer oper ates as an event counter. figure 9-26. timing of operation as exte rnal event counter (8-bit resolution) tmi input cr40 00h tm40 count value 00h 00h 00h 00h interrupt request flag
user?s manual u14826ej4v0ud 118 chapter 10 watchdog timer 10.1 watchdog timer functions the watchdog timer has the following functions: ? watchdog timer ? interval timer caution select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (wdtm). (1) watchdog timer the watchdog timer is used to detect inadvertent program loops. when the inadvertent program loop is detected, a non-maskable interrupt or a reset signal can be generated. table 10-1. inadvertent program loop detection time of watchdog timer inadvertent program loop detection time at f x = 5.0 mhz operation at f cc = 1.0 mhz operation 2 11 1/f clk 2 11 /f x (410 s) 2 11 /f cc (2.05 ms) 2 13 1/f clk 2 13 /f x (1.64 ms) 2 13 /f cc (8.19 ms) 2 15 1/f clk 2 15 /f x (6.55 ms) 2 15 /f cc (32.8 ms) 2 17 1/f clk 2 17 /f x (26.2 ms) 2 17 /f cc (131.1 ms) remarks 1. f clk : f x or f cc 2. f x : system clock oscillation frequency (ceramic/crystal oscillation) 3. f cc : system clock oscillation frequency (rc oscillation) (2) interval timer the interval timer generates an interrupt at an arbitrary preset interval. table 10-2. interval time of watchdog timer interval at f x = 5.0 mhz operation at f cc = 1.0 mhz operation 2 11 1/f clk 2 11 /f x (410 s) 2 11 /f cc (2.05 ms) 2 13 1/f clk 2 13 /f x (1.64 ms) 2 13 /f cc (8.19 ms) 2 15 1/f clk 2 15 /f x (6.55 ms) 2 15 /f cc (32.8 ms) 2 17 1/f clk 2 17 /f x (26.2 ms) 2 17 /f cc (131.1 ms) remarks 1. f clk : f x or f cc 2. f x : system clock oscillation frequency (ceramic/crystal oscillation) 3. f cc : system clock oscillation frequency (rc oscillation)
chapter 10 watchdog timer user?s manual u14826ej4v0ud 119 10.2 watchdog timer configuration the watchdog timer includes the following hardware. table 10-3. configuration of watchdog timer item configuration control registers timer clock selection register 2 (tcl2) watchdog timer mode register (wdtm) figure 10-1. block diagram of watchdog timer internal bus internal bus prescaler selector controller f clk 2 6 f clk 2 8 f clk 2 10 3 7-bit counter clear tmif4 tmmk4 tcl22 tcl21 tcl20 timer clock selection register 2 (tcl2) watchdog timer mode register (wdtm) wdtm4 wdtm3 intwdt maskable interrupt request reset intwdt non-maskable interrupt request f clk 2 4 run remark f clk : f x or f cc
chapter 10 watchdog timer user?s manual u14826ej4v0ud 120 10.3 watchdog timer control registers the following two registers are us ed to control the watchdog timer. timer clock selection register 2 (tcl2) watchdog timer mode register (wdtm) (1) timer clock selecti on register 2 (tcl2) tcl2 sets the watchdog timer count clock. this register is set with an 8-bit memory manipulation instruction. reset input clears tcl2 to 00h. figure 10-2. format of timer clock selection register 2 tcl22 0 0 1 1 tcl21 0 1 0 1 f x /2 4 f x /2 6 f x /2 8 f x /2 10 (313 khz) (78.1 khz) (19.5 khz) (4.88 khz) f cc /2 4 f cc /2 6 f cc /2 8 f cc /2 10 (62.5 khz) (15.6 khz) (3.91 khz) (977 hz) tcl20 0 0 0 0 setting prohibited other than above at f x = 5.0 mhz operation at f cc = 1.0 mhz operation 0 0 0 0 0 tcl22 tcl21 tcl20 tcl2 76 54 symbol address after reset r/w ff42h 00h r/w 3 <2> <1> <0> count clock selection remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : system clock oscillation frequency (rc oscillation)
chapter 10 watchdog timer user?s manual u14826ej4v0ud 121 (2) watchdog timer mode register (wdtm) wdtm sets the operation mode of t he watchdog timer, and enables/disables counting of the watchdog timer. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears wdtm to 00h. figure 10-3. format of watc hdog timer mode register run 0 1 watchdog timer operation selection note 1 stops counting. clears counter and starts counting. wdtm4 watchdog timer operation mode selection note 2 wdtm3 0 1 1 0 1 1 operation stop interval timer mode (generates a maskable interrupt upon overflow occurrence.) note 3 watchdog timer mode 1 (generates a non-maskable interrupt upon overflow occurrence.) watchdog timer mode 2 (starts a reset operation upon overflow occurrence.) 0 0 run 0 0 wdtm4 wdtm3 0 0 0 wdtm <7> 6 5 4 symbol address after reset r/w fff9h 00h r/w 3210 notes 1. once run has been set to 1, it cannot be cleared to 0 by software. ther efore, when counting is started, it cannot be stopped by any means other than reset input. 2. once wdtm3 and wdtm4 have been set to 1, they cannot be cleared to 0 by software. 3. the watchdog timer starts operation as an interval timer when run is set to 1. cautions 1. when the watchdog timer is cleared by setting run to 1, the actual overflow time is up to 0.8% shorter than the time set by th e timer clock selection register 2 (tcl2). 2. to set watchdog timer mode 1 or 2, set wd tm4 to 1 after confirming tmif4 (bit 0 of interrupt request flag register 0 (if0)) bei ng cleared to 0. when watchdog timer mode 1 or 2 is selected with tmif4 set to 1, a non-maskable interrupt is generated upon the completion of rewriting wdtm.
chapter 10 watchdog timer user?s manual u14826ej4v0ud 122 10.4 watchdog timer operation 10.4.1 operation as watchdog timer the watchdog timer detects an inadvert ent program loop when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1. the count clock (inadvertent program loop detection time interval) of t he watchdog timer can be selected by bits 0 to 2 (tcl20 to tcl22) of the timer clock selection register 2 (tcl2). by setting bit 7 (run) of wdtm to 1, the watchdog timer is started. set run to 1 within the set i nadvertent program loop detecti on time interval after the watchdog timer has been started. by setting run to 1, t he watchdog timer can be cleared and start counting. if run is not set to 1, and the inadvertent program loop detection time is exceeded, a system reset signal or a non-maskable interrupt is generated, depending on the va lue of bit 3 (wdtm3) of wdtm. the watchdog timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the watchdog timer before exec uting the stop instruction. caution the actual inadvertent program loop detection time may be up to 0.8% shorter than the set time. table 10-4. inadvertent program loop detection time of watchdog timer tcl22 tcl21 tcl20 at f x = 5.0 mhz operation at f cc = 1.0 mhz operation 0 0 0 2 11 /f x (410 s) 2 11 /f cc (2.05 ms) 0 1 0 2 13 /f x (1.64 ms) 2 13 /f cc (8.19 ms) 1 0 0 2 15 /f x (6.55 ms) 2 15 /f cc (32.8 ms) 1 1 0 2 17 /f x (26.2 ms) 2 17 /f cc (131.1 ms) other than above setting prohibited remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : system clock oscillation frequency (rc oscillation)
chapter 10 watchdog timer user?s manual u14826ej4v0ud 123 10.4.2 operation as interval timer when bits 4 and 3 (wdtm4, wdtm3) of the watchdog timer mode register (wdtm) are set to 0 and 1, respectively, the watchdog timer operates as an interval ti mer that repeatedly generates an interrupt at an interval specified by a preset count value. select a count clock (or interval time) by setting bits 0 to 2 (tcl20 to tcl22) of the time r clock selection register 2 (tcl2). the watchdog timer starts operat ion as an interval timer when the run bit (bit 7 of wdtm) is set to 1. in interval timer mode, the interrupt mask flag (tmmk 4) is valid, and a maskable interrupt (intwdt) can be generated. the priority of intwdt is set as the highest of all the maskable interrupts. the interval timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the interval timer before ex ecuting the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (when watchdog timer mode is selected), interval timer mode is not set unless a reset signal is input. 2. the interval time may be up to 0.8% shorter than the set time when wdtm has just been set. table 10-5. interval time of watchdog timer tcl22 tcl21 tcl20 at f x = 5.0 mhz operation at f cc = 1.0 mhz operation 0 0 0 2 11 /f x (410 s) 2 11 /f cc (2.05 ms) 0 1 0 2 13 /f x (1.64 ms) 2 13 /f cc (8.19 ms) 1 0 0 2 15 /f x (6.55 ms) 2 15 /f cc (32.8 ms) 1 1 0 2 17 /f x (26.2 ms) 2 17 /f cc (131.1 ms) other than above setting prohibited remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : system clock oscillation frequency (rc oscillation)
user?s manual u14826ej4v0ud 124 chapter 11 power-on-clear circuits 11.1 power-on-clear circuit functions the power-on-clear circuits include the following two circuits, which have the following functions. (1) power-on-clear (poc) circuit compares the detection voltage (v poc ) with the power supply voltage (v dd ) and generates an internal reset signal if v dd < v poc . the mask rom versions can select a poc switching circuit, normally operating poc circuit, or normally halted poc circuit by using the ma sk option. when a poc switching ci rcuit is selected, poc operation can be controlled by software (see chapter 18 mask options ). this circuit can operate even in stop mode. (2) low-voltage detection (lvi) circuit compares the detection voltage (v lvi ) with the power supply voltage (v dd ) and generates an interrupt request signal (intlvi1) if v dd < v lvi . eight levels of detection volt age can be selected using software. this circuit stops operation in stop mode. 11.2 power-on-clear circuit configuration figures 11-1 and 11-2 show the block diagr ams of the power-on-clear circuits.
chapter 11 power-on-clear circuits user?s manual u14826ej4v0ud 125 figure 11-1. block diagram of power-on-clear circuit ? + detection voltage source (v poc ) internal reset signal power on clear register 1 (pocf1) internal bus pocof1 pocmk1 pocmk0 v dd v dd p-ch p-ch figure 11-2. block diagram of low-voltage detection circuit lvs12 lvs11 lvs10 lvion1 lvf10 detection voltage source (v lvi ) v dd v dd + ? intlvi1 low-voltage detection register 1 (lvif1) low-voltage detection level selection register 1 (lvis1) p-ch low-voltage detection level selector lvi stop signal (set during stop instruction execution or reset signal generation) p-ch n-ch internal bus
chapter 11 power-on-clear circuits user?s manual u14826ej4v0ud 126 11.3 power-on-clear circuit control registers the following three registers cont rol the power-on-clear circuits. power-on-clear register 1 (pocf1) low-voltage detection register 1 (lvif1) low-voltage detection level se lection register 1 (lvis1) (1) power-on-clear register 1 (pocf1) pocf1 controls poc circuit operation. this register is set with a 1-bit or 8-bit memory manipulation instruction. figure 11-3. format of power-on-clear register 1 symbol 7 6 5 4 3 <2> <1> <0> address after reset r/w pocf1 0 0 0 0 0 poco f1 pocmk1 pocmk0 ffddh 00h note r/w pocof1 poc output detection flag 0 non-generation of reset signal by poc or in cleared state due to a write operation to pocf1 1 generation of reset signal by poc pocmk1 poc reset control 0 generation of reset signal by poc enabled 1 generation of reset signal by poc disabled pocmk0 poc operation control 0 poc operating 1 poc halted note this value is 04h only after a power-on-clear reset. caution for mask rom versions, pocmk0 and pocm k1 are only valid when the poc switching circuit has been selected using a mask option.
chapter 11 power-on-clear circuits user?s manual u14826ej4v0ud 127 (2) low-voltage detecti on register 1 (lvif1) lvif1 controls the operat ion of the lvi circuit. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 11-4. format of low-voltage detection register 1 symbol <7> 6 5 4 3 2 1 <0> address after reset r/w lvif1 lvion1 0 0 0 0 0 0 lvf10 ffdeh 00h r/w note lvion1 lvi operation enable flag 0 lvi disabled 1 lvi enabled lvf10 lvi output detection flag 0 power supply voltage (v dd ) > lvi detection voltage (v lvi ) or operation disabled 1 v dd < v lvi note bit 0 is read only. (3) low-voltage detection level selection register 1 (lvis1) lvis1 selects the level of the detection voltage (v lvi ). this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 11-5. format of low-voltage de tection level selection register 1 symbol 7 6 5 4 3 <2> <1> <0> address after reset r/w lvis1 0 0 0 0 0 lvs12 lvs11 lvs10 ffdfh 00h r/w lvs12 lvs11 lvs10 selection of detection voltage (v lvi ) level note 0 0 0 v lvi0 0 0 1 v lvi1 0 1 0 v lvi2 0 1 1 v lvi3 1 0 0 v lvi4 1 0 1 v lvi5 1 1 0 v lvi6 1 1 1 v lvi7 note see chapter 20 electrical specifications for detection voltage specifications. caution when changing the detection voltage level (v lvi ), an operation stabilization time of about 2 ms is required in order for the lvi output to st abilize. do not, therefore, set the lvi circuit to operation-enable until the operation has stabilized.
chapter 11 power-on-clear circuits user?s manual u14826ej4v0ud 128 11.4 power-on-clear circuit operation 11.4.1 power-on-clear (poc) circuit operation the poc circuit compares the detection voltage (v poc ) with the power supply voltage (v dd ) and generates an internal reset signal if v dd < v poc . for mask rom versions, it is possible to select a po c switching circuit, normally operating poc circuit, or normally halted poc circuit by using a mask option. when a poc switching circuit is selected, poc operation can be controlled by software. only the poc switching circuit is available for the pd78e9860a and 78e9861a (selection cannot be made by mask option). observe the following procedure when switching po c operation using the poc switching circuit. (1) switching from poc stopped to poc operating <1> check that pocmk1 = 1 <2> clear pocmk0 to 0 to put the poc circuit into the operating state <3> wait until the operation stabilization time has elapsed (because t he output signal is unstable, generation of the reset signal via the poc circuit is set to disabled) <4> clear pocmk1 to 0 to enable generation of the reset signal via the poc circuit (2) switching from poc operating to poc stopped <1> set pocmk1 to 1 to disable generation of the reset signal via the poc circuit <2> set pocmk0 to 1 to put the poc circuit into the operation stopped state generation of the reset signal via t he poc circuit can be determined by readi ng the pocof1 flag. when the reset signal is generated via the poc circuit, pocof1 is set to 1. pocof1 is cleared by writing 0 to pocf1 note . when using the poc circui t, clear pocof1 beforehand. note pocof1 is cleared when data is written to any of bits 0 to 2 in the pocf1 register. figures 11-6 to 11-8 show the timing of reset signal generation via the poc circuit. figure 11-6. timing of internal reset signal generation when poc circuit normally operating power supply voltage (v dd ) detection voltage (v poc ) 1.8 v time internal reset signal
chapter 11 power-on-clear circuits user?s manual u14826ej4v0ud 129 figure 11-7. timing of internal reset signal generation when poc circuit normally halted power supply voltage (v dd ) detection voltage (v poc ) 1.8 v time internal reset signal ?h? figure 11-8. timing of internal reset si gnal generation in poc switching circuit power supply voltage (v dd ) detection voltage (v poc ) 1.8 v time internal reset signal pocmk0 pocmk1 wait
chapter 11 power-on-clear circuits user?s manual u14826ej4v0ud 130 11.4.2 operation of low-volt age detection (lvi) circuit the lvi circuit compares the detection voltage (v lvi ) with the power supply voltage (v dd ) and generates an interrupt request signal (intlvi1) if v dd < v lvi (lvi circuit operating). as shown in figure 11-2 block diagram of low -voltage detection circuit, the divided resistors and comparators of the lvi circuit turn off when the reset signal is generated or in stop mode. after reset is released, lvi operation starts when lvion1 (bit 7 of low-voltage detection register 1 (lvif1)) is set. at this time, approximately 2 ms are required until the lvi circuit operation is stabilized. once the lvi operation is started, divided resistors and comparators cannot be off unless the stop instruction or reset signal is generated, even lvion1 is cleared. low-voltage detection is enabled immediately after lvion1 is set again. caution the divider resistor and co mparator of the lvi circuit are tu rned on after reset is released. use one of the following methods to constantly monitor low voltage. <1> low-voltage monitoring by lvfi0 (bit 0 of low- voltage detection register 1 (lvif1)) without using lvi detection interrupt. <2> low-voltage monitoring using lvi detection interrupt. in this case, disable t he lvi operation once, and then enable it (lvion1 = 0 1) before enabling interrupts (lvimk1 = 0). an example of a program in which lo w voltage is constantly m onitored using the lvi detec tion interrupt is shown below. (a) processing when reset mode is released di mov lvis1, #xxh; setting lvi detection voltage set1 lvimk1; lvi interrupt disabled set1 lvion1; lvi operation enabled call !wait_2ms; 2 ms wait clr1 lviif1; clr1 lvion1; lvi operation disabled set1 lvion1; lvi operation enabled clr1 lvimk1; lvi interrupt enabled ei (b) processing when stop mode is released set1 lvimk1; lvi interrupt disabled stop call !wait; total 2 ms wait, combined with oscillation stabilization time clr1 lviif1 clr1 lvion1; lvi operation disabled set1 lvion1; lvi operation enabled clr1 lvimk1; lvi interrupt enabled ei
chapter 11 power-on-clear circuits user?s manual u14826ej4v0ud 131 (c) processing to enable lvi interr upt again after lvi interrupt servicing set1 lvimk1; lvi interrupt disabled clr1 lvion1; lvi operation disabled set1 lvion1; lvi operation enabled clr1 lvimk1; lvi interrupt enabled ei figure 11-9 shows the lvi circuit operation timing. figure 11-9. lvi circuit operation timing vectored interrupt vectored interrupt does not occur power supply voltage (v dd ) detection voltage (v lvi ) 1.8 v lvion1 ie intlvi1 lviif1 lvimk1 2 ms caution the low-voltage detection interrupt request fl ag (lviif1) is set at the rising edge of the lvi circuit comparator output signal (intlvi1). therefore, the power supply voltage (v dd ) becomes lower than the detection voltage (v lvi ) during lvi operation, and if that state continues after intlvi1 generation, lviif1 is not set. a fter low-voltage detect ion, when set as v dd > v lvi and then v dd < v lvi again, lviif1 is set.
user?s manual u14826ej4v0ud 132 chapter 12 bit sequential buffer 12.1 bit sequential buffer functions the pd789860, 789861 subseries have an on-chip bit sequential buffer of 8 bits 8 bits = 16 bits. the functions of the bit s equential buffer are shown below. if the value of the bit sequential buffe r 10 data register (bsfrl10, bsfrh10) is shifted 1 bit to the lower side, the lsb can be output to the port at the same time. it is possible to write to bsfrl10 and bsfrh10 using an 8-bit or 16-bit memory manipulation instruction (reading is not possible). overwriting is enabled during a shift operation on the higher 8 bits (bsfrh 10) only (the period in which shift clock is low level). 12.2 bit sequential buffer configuration the bit sequential buffer incl udes the following hardware. table 12-1. configuration of bit sequential buffer item configuration data register bit sequential buffer: 8 bits 8 bits = 16 bits control register bit sequential buffer output control register 10 (bsfc10) port mode register 2 (pm2) port 2 (p2) figure 12-1. block diagram of bit sequential buffer bit sequential buffer output control register 10 (bsfc10) internal bus timer 40 match interrupt request signal bsfrh10 bsfrl10 internal bus bsfe10 bsfo/p20/ tmo p20 output latch pm20
chapter 12 bit sequential buffer user?s manual u14826ej4v0ud 133 12.3 bit sequential buffer control register the bit sequential buffer is controlled by the following three registers. ? bit sequential buffer output c ontrol register 10 (bsfc10) ? port mode register 2 (pm2) ? port 2 (p2) (1) bit sequential buffer output control register 10 (bsfc10) bsfc10 controls the operation of the bit sequential buffer. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 12-2. format of bit sequentia l buffer output control register 10 symbol 7 6 5 4 3 2 1 <0> address after reset r/w bsfc10 0 0 0 0 0 0 0 bsfe10 ff60h 00h r/w bsfe10 bit sequential buffer operation control 0 operation disabled 1 operation enabled (2) port mode register 2 (pm2) pm2 sets port 2 to input/output in 1-bit units. when using the p20/tmo/bsfo pin as a data output of the bit sequential buffer, clear the pm20 and p20 output latch to 0. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 12-3. format of port mode register 2 symbol 7 6 5 4 3 2 1 0 address after reset r/w pm2 1 1 1 1 1 1 pm21 pm20 ff22h ffh r/w pm20 p20 pin input/output mode 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 12 bit sequential buffer user?s manual u14826ej4v0ud 134 12.4 bit sequential buffer operation set as follows to operate the bit sequential buffer. <1> set values to bit sequential buffer 10 data registers l and h (bsfrl10, bsfrh10) <2> set the bit sequential buffer to operation enabled (bsfe10 = 1) if the lsb of bsfrl10 is being out put at p20/bsfo/tmo, set p20 to output mode (pm20 = 0) and the output latch of p20 to 0 <3> start the clock operation if the clock is input before the bit sequent ial buffer starts operation, the output time of the start bit may be shorter than one cycle of the clock when output comm ences, as shown in the figure below. 2aaah 0aaah 5555h 1555h t0 t1 t2 t1< t0 t2 = t0 bsfe10 timer 40 match signal bsfrl10, bsfrh10 bit sequential buffer output figure 12-4 shows the operation timi ng of the bit sequential buffer. figure 12-4. operation timing of bit sequential buffer 2aaah 0aaah 1555h bsfe10 timer 40 match signal bsfrl10, bsfrh10 bit sequential buffer output undefined 5555h 555h 2aah cautions 1. even if data is wri tten to the data register while the bit sequential buffer is operating, the shift clock (timer 40 match signal) will not stop. data should therefore be written to the data register when the shift clock is low level. 2. the value of the data regi ster is undefined after a shift. remark : undefined
user's manual u14826ej4v0ud 135 chapter 13 key return circuit 13.1 key return circuit function in stop mode, this circuit generates a key return inte rrupt (intkr1) by inputting a p40/kr10 to p43/kr13 falling edge. cautions 1. the key return interrupt is a non-maskable interrupt that is effective only in stop mode. in addition, p40/kr10 to p43/kr13 key input cannot be performed by mask control. 2. the key return signal cannot be detected even if a falling edge is generated on the other key return pins while even one of the key retu rn pins (p40/kr10 to p43/kr13) is low. 13.2 key return circuit configuration and operation figure 13-1 shows the block diagram of the key return ci rcuit. figure 13-2 shows the generation timing of the key return interrupt (intkr1). figure 13-1. block diagra m of key return circuit key return interrupt (intkr1) falling edge detector p43/kr13 p40/kr10 p41/kr11 p42/kr12 stop mode figure 13-2. generation timi ng of key return interrupt stop signal p4n/kr1n intkr1 remark n = 0 to 3
user's manual u14826ej4v0ud 136 chapter 14 interrupt functions 14.1 interrupt function types the following two types of in terrupt functions are used. (1) non-maskable interrupts this interrupt is acknowledged unconditionally even if interrupts are disabled. it does not undergo interrupt priority control and is given top priori ty over all other interrupt requests. a standby release signal is generated. there are one external source and one inter nal source of non-maskable interrupts. (2) maskable interrupts these interrupts undergo mask control. if two or more interrupt requests are simultaneously generated, each interrupt has a predetermined priori ty as shown in table 14-1. a standby release signal is generated. there are five internal sour ces of maskable interrupts.
chapter 14 interrupt functions user?s manual u14826ej4v0ud 137 14.2 interrupt sources and configuration there are a total of 7 non-maskable and maskable interrupt sources (see table 14-1 ). table 14-1. interrupt sources interrupt source interrupt type priority note 1 name trigger internal/external vector table address basic configuration type note 2 intkr1 key return input falling edge detection external 0002h non-maskable interrupt ? intwdt watchdog timer overflow (when watchdog timer mode 1 is selected) (a) 0 intwdt watchdog timer overflow (when interval timer mode is selected) 0004h 1 inttm30 generation of match signal for 8-bit timer 30 0006h 2 inttm40 generation of match signal for 8-bit timer 40 0008h 3 intlvi1 lvi interrupt request signal 000ah maskable interrupt 4 intee0 eeprom write termination signal internal 000ch (b) notes 1. priority is the priority order when several maskabl e interrupt requests are generated at the same time. 0 is the highest and 4 is the lowest. 2. basic configuration types (a) and (b) correspond to (a) and (b) in figure 14-1. remark there are two interrupt sources for the wa tchdog timer (intwdt): non-maskable interrupts and maskable interrupts (internal). either one (but not both) should be sele cted for actual use.
chapter 14 interrupt functions user?s manual u14826ej4v0ud 138 figure 14-1. basic configuration of interrupt function (a) external/internal non-maskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal if: interrupt request flag ie: interrupt enable flag mk: interrupt mask flag
chapter 14 interrupt functions user?s manual u14826ej4v0ud 139 14.3 interrupt function control registers the interrupt functions are controlled by the following three types of registers. interrupt request flag register 0 (if0) interrupt mask flag register 0 (mk0) program status word (psw) table 14-2 lists interrupt requests, the correspondi ng interrupt request flags, and interrupt mask flags. table 14-2. interrupt request signals and corresponding flags interrupt request signal interrupt request flag interrupt mask flag intwdt inttm30 inttm40 intlvi1 intee0 tmif4 tmif30 tmif40 lvif1 eeif0 tmmk4 tmmk30 tmmk40 lvimk1 eemk0 (1) interrupt request flag register 0 (if0) an interrupt request flag is set to 1 when the co rresponding interrupt request is issued, or when the instruction is executed. it is cleared to 0 by ex ecuting an instruction when the interrupt request is acknowledged or when a reset signal is input. if0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears if0 to 00h. figure 14-2. format of interrupt request flag register 0 if 0 1 interrupt request flag no interrupt request signal has been issued. an interrupt request signal has been issued; an interrupt request status. 00 0 eeif0 tmif30 tmif40 lviif1 tmif4 if0 7 6 5 <4> <3> <2> <1> <0> symbol address after reset r/w ffe0h 00h r/w cautions 1. be sure to clear bits 5 to 7 to 0. 2. the tmif4 flag can be read- and writ e-accessed only when the watchdog timer is being used as an interval ti mer. it must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2.
chapter 14 interrupt functions user?s manual u14826ej4v0ud 140 (2) interrupt mask flag register 0 (mk0) the interrupt mask flag is used to enable and di sable the corresponding maskable interrupts. mk0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets mk0 to ffh. figure 14-3. format of interrupt mask flag register 0 mk 0 1 interrupt servicing control enables servicing servicing. disables servicing servicing. 11 1 eemk0 tmmk30 tmmk40 lvimk1 tmmk4 mk0 7 6 5 <4> <3> <2> <1> <0> symbol address after reset r/w ffe4h ffh r/w cautions 1. be sure to set bits 5 to 7 to 1. 2. the tmmk4 flag can be read- and write-accessed only when the watchdog timer is being used as an interval timer. it must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. (3) program status word (psw) the program status word is used to hol d the instruction executi on result and the current st atus of the interrupt requests. the ie flag, used to enable and dis able maskable interrupts, is mapped to psw. psw can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated instructions (ei and di). when a vectored interrupt is ack nowledged, the psw is automatically saved to a stack, and the ie flag is reset to 0. reset input sets psw to 02h. figure 14-4. program status word configuration ie z 0 ac 0 0 1 cy psw symbol after reset 02h 76543210 ie 0 1 disabled enabled whether to enable/disable interrupt acknowledgment used in the execution of ordinary instructions
chapter 14 interrupt functions user?s manual u14826ej4v0ud 141 14.4 interrupt servicing operation 14.4.1 non-maskable interrupt request acknowledgment operation the non-maskable interrupt request is unconditionally ack nowledged even when interrupts are disabled. it is not subject to interrupt priority control and takes precedence over all other interrupts. when the non-maskable interrupt request is acknowledged, psw and pc are saved to the stack in that order, the ie flag is reset to 0, the contents of the vector t able are loaded to the pc, and t hen program execution branches. figure 14-5 shows the flowchart from non-maskable inte rrupt request generation to acknowledgment. figure 14-6 shows the timing of non-maskable interrupt request a cknowledgment. figure 14-7 shows the acknowledgment operation if multiple non-mask able interrupts are generated. caution the pd789860 and 789861 subseries have two non-maskab le interrupt sources. therefore, during execution of a non-maskable interrupt ser vicing program, a new non-maskable interrupt request is not acknowledged until the reti instruct ion is executed. be su re to execute the reti instruction after the interrupt ser vicing program has been executed. when using the watchdog timer as a non-maskab le interrupt, push the address of restore destination before executing the re ti instruction. if the reti instruction is executed without pushing the restore destination, the program will jump to an illegal address. a program example is shown below. program example in which watchdog timer is used as non-maskable interrupt and program branches to reset vector when interrupt occurs xvect cseg at 0000h dw ireset ;(00) reset dw ikr ;(02) keyreturn dw iwdt ;(04) intwdt : xrst cseg at 0080h ireset: di movw ax,#0feffh movw sp, ax : : iwdt: (interrupt servicing) movw ax,#0080h push ax reti
chapter 14 interrupt functions user?s manual u14826ej4v0ud 142 figure 14-5. flowchart from non-maskable interrupt request generation to acknowledgment (intwdt) start wdtm4 = 1 (watchdog timer mode is selected) interval timer no wdt overflows no yes reset processing no yes yes interrupt request is generated interrupt servicing is started wdtm3 = 0 (non-maskable interrupt is selected) wdtm: watchdog timer mode register wdt: watchdog timer figure 14-6. timing of non-maskable interrupt request acknowledgment instruction instruction saving psw and pc, and jump to interrupt servicing interrupt servicing program cpu processing wdtif figure 14-7. acknowledgment of non-maskable interrupt request first interrupt servicing reti instruction execution second interrupt servicing reti instruction execution nmi request (second) nmi request (first) main routing
chapter 14 interrupt functions user?s manual u14826ej4v0ud 143 14.4.2 maskable interrupt re quest acknowledgment operation a maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. a vect ored interrupt request is a cknowledged in the interrupt enabled status (when the ie flag is set to 1). the time required to start the interrupt servicing afte r a maskable interrupt request has been generated is shown in table 14-3. see figures 14-9 and 14-10 for the inte rrupt request acknowledgment timing. table 14-3. time from generation of maskable interrupt request to servicing minimum time maximum time note 9 clocks 19 clocks note the wait time is maximum when an interrupt request is generated imm ediately before bt and bf instruction. remark 1 clock: (f cpu : cpu clock) when two or more maskable interrupt requests are generat ed at the same time, they are acknowledged starting from the interrupt request assigned the highest priority. a pending interrupt is acknowledged when a status in which it can be acknowledged is set. figure 14-8 shows the algorithm of interrupt request acknowledgment. when a maskable interrupt request is a cknowledged, the contents of the psw and pc are saved to the stack in that order, the ie flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the pc, and execution branches. to return from interrupt servic ing, use the reti instruction. 1 f cpu
chapter 14 interrupt functions user?s manual u14826ej4v0ud 144 figure 14-8. interrupt request acknowledgment processing algorithm start if = 1? mk = 0? ie = 1? vectored interrupt servicing yes (interrupt request generated) yes yes no no no interrupt request pending interrupt request pending if: interrupt request flag mk: interrupt mask flag ie: flag to control maskable interrupt reques t acknowledgment (1 = enable, 0 = disable) figure 14-9. interrupt request ackno wledgment timing (example of mov a, r) clock cpu interrupt mov a, r saving psw and pc, jump to interrupt servicing 8 clocks interrupt servicing program if an interrupt request flag ( if) is set before an instruction clock n (n = 4 to 10) under execution becomes n ? 1, the interrupt is acknowledged after the instruction under execution is complete . figure 14-9 shows an example of the interrupt request acknowledgment timing for an 8-bit data transfe r instruction mov a, r. since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgment processing is performed after the mo v a, r instruction is executed.
chapter 14 interrupt functions user?s manual u14826ej4v0ud 145 figure 14-10. interrupt request ack nowledgment timing (when interrupt request flag is set at last clock during instruction execution) saving psw and pc, jump to interrupt servicing 8 clocks interrupt servicing program clock cpu interrupt nop mov a, r if an interrupt request flag ( if) is set at the last clock of the instru ction, the interrupt a cknowledgment processing starts after the next instruction is executed. figure 14-10 shows an example of the in terrupt acknowledgment timing for an in terrupt request flag that is set at the second clock of nop (2-clock instruction). in this ca se, the mov a, r instruction after the nop instruction is executed, and then the interrupt ack nowledgment processing is performed. caution interrupt requests will be held pending while interrupt request flag register 0 (if0) or interrupt mask flag register 0 (mk0) is being accessed.
chapter 14 interrupt functions user?s manual u14826ej4v0ud 146 14.4.3 multiple interrupt servicing multiple interrupt servicing in whic h another interrupt is acknowledged while an interrupt is being serviced can be performed using a priority order system. when two or more interrupts are generated at onc e, interrupt servicing is performed according to the priority assi gned to each interrupt request in advance (see table 14-1 ). figure 14-11. example of multiple interrupts example 1. a multiple interrupt is acknowledged intyy ei main processing ei intyy servicing intxx servicing reti ie = 0 intxx reti ie = 0 during interrupt intxx servicing, interrupt request int yy is acknowledged, and multiple interrupts are generated. the ei instruction is iss ued before each interrupt request acknowledgmen t, and the interrupt request acknowledgment enable state is set. example 2. multiple interrupts are not generated because interrupts are not enabled intyy ei main processing reti intyy servicing intxx servicing ie = 0 intxx reti intyy is held pending ie = 0 because interrupts are not enabled in inte rrupt intxx servicing (the ei instruct ion is not issued), interrupt request intyy is not acknowledged, and mult iple interrupts are not generated. the intyy request is held pending and acknowledged after the intxx servicing is performed. ie = 0: interrupt request acknowledgment disabled
chapter 14 interrupt functions user?s manual u14826ej4v0ud 147 14.4.4 interrupt request pending some instructions may keep pending t he acknowledgment of an instruction request until the completion of the execution of the next instru ction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution. the following shows such instructions (interrupt request pending instruction). ? manipulation instruction for inte rrupt request flag register 0 (if0) ? manipulation instruction for inte rrupt mask flag register 0 (mk0)
user?s manual u14826ej4v0ud 148 chapter 15 standby function 15.1 standby function and configuration 15.1.1 standby function the standby function is used to reduce the power consum ption of the system and can be effected in the following two modes: (1) halt mode this mode is set when the halt instru ction is executed. ha lt mode stops the operati on clock of the cpu. the system clock oscillator continues oscillating. th is mode does not reduce the current consumption as much as stop mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) stop mode this mode is set when the stop instruction is exec uted. the stop mode stops the main system clock oscillator and stops the entire system. the current consumpti on of the cpu can be s ubstantially reduced in this mode. the low voltage (v dd = 1.8 v max.) of the data memory can be reta ined. therefore, this mode is useful for retaining the contents of the data memory at an extremely low current consumption. stop mode can be released by an interrupt request, so that this mode can be used for intermittent operation. however, some time is required until the system clock oscilla tor stabilizes after stop mode has been released. if processing must be resumed immediatel y by using an interrupt r equest, therefore, use the halt mode. in both modes, the previous contents of the registers, flags, and data memo ry before setting standby mode are all retained. in addition, the statuses of the output latches of the i/o ports and output buffers are also retained. caution to set stop mode, be sure to stop the opera tions of the peripheral ha rdware, and then execute the stop instruction.
chapter 15 standby function user?s manual u14826ej4v0ud 149 15.1.2 standby function control register the wait time after stop mode is released upon interrupt request until the oscillation st abilizes is controlled with the oscillation stabilization time selection register (osts) note . osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, the oscillation stabilization time after r eset release varies for each product not depending on the osts. pd789860: oscillation stabilization time can be selected from 2 15 /f x or 2 17 /f x by mask option. pd78e9860a: oscillation stabilization time is fixed to 2 15 /f x and cannot be selected by mask option. pd789861, 78e9861a: oscillation stabilization time is fixed to 2 7 /f cc and cannot be selected by mask option. note pd789860 subseries only. there is no oscillation stabilization time selection register in the pd789861 subseries. the oscillation stabilization time of the pd789861 subseries is fixed at 2 7 /f cc . figure 15-1. format of oscillation st abilization time selection register osts2 0 0 1 osts1 0 1 0 2 12 /f x 2 15 /f x 2 17 /f x (819 s) (6.55 ms) (26.2 ms) osts0 0 0 0 setting prohibited oscillation stabilization time selection other than above 00 0 0 osts1 osts2 0 osts0 osts 7 654 32 10 symbol address after reset r/w fffah 04h r/w caution the wait time after stop mode is released does not include th e time from stop mode release to clock oscillation start (?a? in the figure below) , regardless of release by reset input or by interrupt generation. stop mode release x1 pin voltage waveform a remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 15 standby function user?s manual u14826ej4v0ud 150 15.2 standby function operation 15.2.1 halt mode (1) halt mode halt mode is set by execut ing the halt instruction. the operation statuses in halt mode are shown in the following table. table 15-1. operation statuses in halt mode item halt mode operation status system clock system clock oscillation enabled clock supply to cpu stopped cpu operation stopped eeprom operation enabled note 1 port (output latch) remains in the st ate existing before halt mode has been set tm30 operation enabled 8-bit timer tm40 operation enabled watchdog timer operation enabled poc operation enabled note 2 power-on-clear circuit lvi operation enabled bit sequential buffer operation enabled key return circuit operation stopped notes 1. halt mode can be set after ex ecuting a write instruction. 2. if a poc switching circuit is selected by the ma sk option and the poc circuit is set to operation enabled by software or if poc circuit normally oper ating is selected by the mask option (see chapter 18 mask options regarding mask options).
chapter 15 standby function user?s manual u14826ej4v0ud 151 (2) releasing halt mode halt mode can be released by the following three sources: (a) releasing by unmasked interrupt request halt mode is released by an unm asked interrupt request. in this case, if interrupt request acknowledgment is enabled, vectored in terrupt servicing is performed. if interrupt acknowledgment is disabled, the instruction at the next address is executed. figure 15-2. releasing halt mode by interrupt halt instruction standby release signal wait wait halt mode operating mode operating mode clock oscillation remarks 1. the broken lines indicate the case where the interrupt request t hat has released standby mode is acknowledged. 2. the wait time is as follows: ? when vectored interrupt servici ng is performed: 9 to 10 clocks ? when vectored interrupt servicing is not performed: 1 to 2 clocks (b) releasing by non-maskable interrupt request halt mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt servicing is performed.
chapter 15 standby function user?s manual u14826ej4v0ud 152 (c) releasing by reset input when halt mode is released by t he reset signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution starts. figure 15-3. releasing halt mode by reset input halt instruction reset signal wait note reset period halt mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation note in the pd789860, 2 15 /f x or 2 17 /f x can be selected by using the mask option. in the pd78e9860a, 2 15 /f x : 6.55 ms (@f x = 5.0 mhz operation) in the pd789861 and 78e9861a, 2 7 /f cc : 128 s (@f cc = 1.0 mhz operation) remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : system clock oscillation frequency (rc oscillation) table 15-2. operation after releasing halt mode releasing source mk ie operation 0 0 executes next address instruction. 0 1 executes interrupt servicing. maskable interrupt request 1 retains halt mode. non-maskable interrupt request ? executes interrupt servicing. reset input ? ? reset processing : don?t care
chapter 15 standby function user?s manual u14826ej4v0ud 153 15.2.2 stop mode (1) setting and operation st atus of stop mode stop mode is set by execut ing the stop instruction. caution because standby mode can be released by an interrupt request si gnal, standby mode is released as soon as it is set if there is an in terrupt source whose interrupt request flag is set and interrupt mask flag is reset. when st op mode is set, therefore, halt mode is set immediately after the stop in struction has been executed, th e oscillation stabilization time elapses, and then the operation mode is set. the operation statuses in stop mode are shown in the following table. table 15-3. operation statuses in stop mode item stop mode operation status system clock system clock oscillation stopped clock supply to cpu stopped cpu operation stopped eeprom operation stopped port (output latch) remains in the st ate existing before stop mode has been set tm30 operation enabled note 1 8-bit timer tm40 operation enabled note 2 watchdog timer operation stopped poc operation enabled note 3 power-on-clear circuit lvi operation stopped bit sequential buffer operation enabled note 4 key return circuit operation enabled notes 1. operation enabled only when cascade connected with tm40 (external clo ck selected for count clock) 2. operation enabled only when external cl ock is selected for count clock 3. if a poc switching circuit is selected by the mask option and the poc circuit is set to operation enabled by software or if poc circuit normally oper ating is selected by the mask option (see chapter 18 mask options regarding mask options). 4. operation enabled only when external clock is se lected for tm40 count clock and inttm40 occurs
chapter 15 standby function user?s manual u14826ej4v0ud 154 (2) releasing stop mode stop mode can be released by the following two sources: (a) releasing by unmasked interrupt request stop mode is released by an unmask ed interrupt request. in this case, vectored interrupt servicing is performed if interrupt acknowledgment is enabled after the oscillation stabilization time has elapsed. if interrupt acknowledgment is disabled, the in struction at the next address is executed. figure 15-4. releasing stop mode by interrupt stop instruction standby release signal wait note (time set by osts) stop mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation note there is no osts in the pd789861 subseries, and the wait is fixed at 2 7 /f cc . remark the broken lines indicate the case where the interrupt request t hat has released standby mode is acknowledged.
chapter 15 standby function user?s manual u14826ej4v0ud 155 (b) releasing by reset input when stop mode is released by the reset signal, t he reset operation is performed after the oscillation stabilization time has elapsed. figure 15-5. releasing stop mode by reset input stop instruction reset signal wait note stop mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation reset period note in the pd789860, 2 15 /f x or 2 17 /f x can be selected by using the mask option. in the pd78e9860a, 2 15 /f x : 6.55 ms (@f x = 5.0 mhz operation) in the pd789861 and 78e9861a, 2 7 /f cc : 128 s (@f cc = 1.0 mhz operation) remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : system clock oscillation frequency (rc oscillation) table 15-4. operation after releasing stop mode releasing source mk ie operation 0 0 executes next address instruction. 0 1 executes interrupt servicing. maskable interrupt request 1 retains stop mode. reset input ? ? reset processing : don?t care
user?s manual u14826ej4v0ud 156 chapter 16 reset function the following three operations are av ailable to generate reset signals. (1) external reset input by reset signal input (2) internal reset by watchdog timer inadvertent program loop time detection (3) internal reset by comparison of poc circuit power supply voltage and detection voltage external reset and internal reset have no functional differenc es. in both cases, program execution starts at the address at 0000h and 0001h by reset signal input. when a low level is input to the reset pin, the watchdog timer overflows, or poc circuit voltage is detected, a reset is applied and each hardware is set to the status shown in table 16-1. each pin is high impedance during reset input or during the oscillation stabilizat ion time just after reset clear. when a high level is input to the r eset pin, the reset is cleared and progr am execution is started after the oscillation stabilization time has elapsed. the reset appli ed by the watchdog timer overfl ow is automatically cleared after reset, and program execution is started afte r the oscillation stabilization time has elapsed (see figures 16-2 to 16-4 ). cautions 1. for an external reset, input a low level of 10 s or more to the reset pin. 2. when stop mode is cleared by reset, the st op mode contents are he ld during reset input. however, the port pins become high impedance. figure 16-1. block diagram of reset function reset interrupt function count clock reset controller watchdog timer poc circuit over- flow reset signal stop
chapter 16 reset function user?s manual u14826ej4v0ud 157 figure 16-2. reset timing by reset input x1, cl1 reset internal reset signal port pin normal operation reset period (oscillation stops) oscillation stabilization time wait normal operation (reset processing) delay delay hi-z figure 16-3. reset timing by watchdog timer overflow x1, cl1 internal reset signal port pin watchdog timer overflow normal operation reset period (oscillation continues) oscillation stabilization time wait normal operation (reset processing) hi-z figure 16-4. reset timing by reset input in stop mode x1, cl1 reset internal reset signal port pin hi-z delay delay stop instruction execution normal operation stop status (oscillation stops) reset period (oscillation stops) oscillation stabilization time wait normal operation (reset processing)
chapter 16 reset function user?s manual u14826ej4v0ud 158 table 16-1. status of hardware after reset hardware status after reset program counter (pc) note 1 the contents of the reset vector table (0000h, 0001h) are set stack pointer (sp) undefined program status word (psw) 02h eeprom write control register (eewc10) 08h data memory undefined note 2 ram general-purpose registers undefined note 2 ports (p0, p2) (output latch) 00h port mode registers (pm0, pm2) ffh processor clock control register (pcc) 02h oscillation stabilization time selection register (osts) note 3 04h timer counters (tm30, tm40) 00h compare registers (cr30, cr40, crh40) undefined mode control registers (tmc30, tmc40) 00h 8-bit timer carrier generator output control register (tca40) 00h timer clock selection r egister s (tcl2) 00h watchdog timer mode register (wdtm) 00h power-on-clear register (pocf1) 00h note 4 low-voltage detection register (lvif1) 00h power-on-clear circuit low-voltage detection level selection register (lvis1) 00h data registers (bsfrl10, bsfrh10) undefined bit sequential buffer output control register (bsfc10) 00h request flag register (if0) 00h interrupts mask flag register (mk0) ffh notes 1. while a reset signal is being input, and during the osc illation stabilization time wa it, the contents of the pc will be undefined, while the remainder of the hardware will be the same as after the reset. 2. in standby mode, the ram enter s the hold state after a reset. 3. pd789860 subseries only 4. this value is 04h only after a power-on-clear reset.
user?s manual u14826ej4v0ud 159 chapter 17 pd78e9860a, 78e9861a eeprom versions in the pd789860, 789861 subseries include the pd78e9860a and 78e9861a. the pd78e9860a replaces the internal rom of the pd789860 with eeprom. the pd78e9861a replaces the internal rom of the pd789861 with eeprom. the differences between the pd78e9860a, 78e9861a and the mask rom versions are shown in table 17-1. table 17-1. differences between pd78e9860a, 78e9861a and mask rom versions part number eeprom versions mask rom versions item pd78e9860a pd78e9861a pd789860 pd789861 rom structure eeprom mask rom program memory rom capacity 4 kb high-speed ram 128 bytes internal memory data memory eeprom 32 bytes system clock ceramic/crystal oscillation rc oscillation ceramic/crystal oscillation rc oscillation ic pin not provided provided v pp pin provided not provided p40 to p43 pull-up resistor by mask option not provided provided poc circuit selection by ma sk option not provided provided oscillation stabilization time after stop mode is released by interrupt request can select 2 12 /f x , 2 15 /f x , or 2 17 /f x by osts register 2 7 /f cc can select 2 12 /f x , 2 15 /f x , or 2 17 /f x by osts register 2 7 /f cc oscillation stabilization time after stop mode release by reset or reset release via poc circuit 2 15 /f x 2 7 /f cc can select 2 15 /f x or 2 17 /f x by mask option 2 7 /f cc power supply voltage (v dd ) 1.8 to 5.5 v 1.8 to 3.6 v 1.8 to 5.5 v 1.8 to 3.6 v electrical specifications varies depending on eeprom or mask rom version. caution there are differences in noise immunity and noise radiation between the eeprom and mask rom versions. when pre-producing an appli cation set with the eeprom version and then mass-producing it with the mask rom version, be sure to conduct suffici ent evaluations for the commercial samples (not engineering samples) of the mask rom version.
chapter 17 pd78e9860a, 78e9861a user?s manual u14826ej4v0ud 160 17.1 eeprom features (program memory) the on-chip program memory in the pd78e9860a and 78e9861a is eeprom. this chapter describes the functions of the eeprom incorporated in t he program memory area. for the eeprom incorporated in data memory, see chapter 5 eeprom (data memory) . eeprom can be written with the pd78e9860a and 78e9861a mounted on the target system (on-board). connect the dedicated flash writer (flas hpro iii (part no. fl-pr3, pg-fp3)/flashpr o iv (part no. fl-pr4, pg-fp4)) to the host machine and target system to write to eeprom. remark fl-pr3 and fl-pr4 are products of naito dens ei machida mfg. co., ltd (tel +81-45-475-4191). programming using eeprom has the following advantages. software can be modified after the microcont roller is solder-mounted on the target system. distinguishing software facilities sm all-quantity, varied model production easy data adjustment when starting mass production 17.1.1 programming environment the following shows the environment required for pd78e9860a, 78e9861a eeprom programming. when flashpro iii (part no. fl-pr3, pg-fp3) or flashpro iv (part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, a host machine is required to contro l the dedicated flash progra mmer. communication between the host machine and flash programmer is performed via rs-232c/usb (rev. 1.1). for details, refer to the manuals for flashpro iii/flashpro iv. remark usb is supported by flashpro iv only. figure 17-1. environment for writing program to eeprom (program memory) host machine rs-232c usb dedicated flash programmer pd78e9860a, pd78e9861a v pp v dd v ss reset pseudo 3-wire
chapter 17 pd78e9860a, 78e9861a user?s manual u14826ej4v0ud 161 17.1.2 communication mode use the communication mode shown in table 17-2 to perform communication between the dedicated flash programmer and pd78e9860a, 78e9861a. table 17-2. communication mode list type setting note 1 cpu clock note 1 communication mode comm port sio clock in flashpro on target board multiple rate pins used number of v pp pulses pseudo 3-wire port a (pseudo- 3 wire) 100 hz to 1 khz 1, 2, 4, 5 mhz notes 2, 3 1 to 5 mhz note 2 1.0 p02 (serial data input) p01 (serial data output) p00 (serial clock input) 12 notes 1. be sure to use in flashpro (system clock is supplied from a dedicat ed flash writer) with the pd78e9861a. 2. the possible setting range differs dependi ng on the voltage. for details, see chapter 20 electrical specifications . 3. 2 or 4 mhz only with flashpro iii figure 17-2. communication mode selection format 10 v v ss v dd v pp v dd v ss reset 12 v pp pulse n
chapter 17 pd78e9860a, 78e9861a user?s manual u14826ej4v0ud 162 figure 17-3. example of connecti on with dedicated flash programmer (a) pseudo 3-wire ( pd78e9860a) dedicated flash programmer vpp1 vdd reset sck so si clk note gnd v pp v dd reset p00 (serial clock) p02 (serial input) p01 (serial output) x1 v ss pd78e9860a (b) pseudo 3-wire ( pd78e9861a) dedicated flash programmer vpp1 vdd reset sck so si clk gnd v pp v dd reset p00 (serial clock) p02 (serial input) p01 (serial output) p03 v ss pd78e9861a note when supplying the system clock from a dedicated flas h writer, connect the clk and x1 pins and cut off the resonator on the board. when using the clock oscillated by the on-boar d resonator, do not connect the clk pin. caution the v dd pin, if already connected to the power suppl y, must be connected to the vdd pin of the dedicated flash programmer. when using the power supply connected to the vdd pin, supply voltage before starting programming.
chapter 17 pd78e9860a, 78e9861a user?s manual u14826ej4v0ud 163 if flashpro iii (part no. fl-pr3, pg-fp3)/flashpro iv ( part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, the following signals are generated for the pd78e9860a, 78e9861a. for details, refer to the manual of flashpro iii/flashpro iv. table 17-3. pin connection list signal name i/o pin function pin name pseudo 3-wire vpp1 output write voltage v pp vpp2 ? ? ? vdd i/o v dd voltage generation/voltage monitoring v dd note gnd ? ground v ss x1 ( pd78e9860a) clk output clock output p03 ( pd78e9861a) reset output reset signal reset si input receive signal p01 so output transmit signal p02 sck output transfer clock p00 hs input handshake signal ? note v dd voltage must be supplied befor e programming is started. remark : pin must be connected. : if the signal is supplied on the target board, pin does not need to be connected. : pin does not need to be connected.
chapter 17 pd78e9860a, 78e9861a user?s manual u14826ej4v0ud 164 17.1.3 on-board pin processing when performing programming on the tar get system, provide a connector on t he target system to connect the dedicated flash programmer. an on-board function that allows switching between normal operati on mode and eeprom programming mode may be required in some cases. in normal operation mode, input 0 v to the v pp pin. in eeprom programming mode, a write vo ltage of 10.0 v (typ.) is supplied to the v pp pin, so perform either of the following. (1) connect a pull-down resistor rv pp = 10 k ? to the v pp pin. (2) use the jumper on t he board to switch the v pp pin input to either the progr ammer or directly to gnd. a v pp pin connection example is shown below. figure 17-4. v pp pin connection example pd78e9860a, 78e9861a v pp connection pin of dedicated flash programmer pull-down resistor ( rv pp ) the following shows the pins us ed by the serial interface. serial interface pins used pseudo 3-wire p02, p01, p00 when connecting the dedicated flash programmer to a serial interface pin that is connected to another device on- board, signal conflict or abnormal operation of the other device may occur. care must therefore be taken with such connections.
chapter 17 pd78e9860a, 78e9861a user?s manual u14826ej4v0ud 165 (1) signal conflict if the dedicated flash programmer (output ) is connected to a serial interfac e pin (input) that is connected to another device (output), a signal conflict occurs. to prevent this , isolate the connection with the other device or set the other device to the output high impedance status. figure 17-5. signal conflict (input pin of serial interface) input pin signal conflict connection pin of dedicated flash programmer other device output pin in the eeprom programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict; therefore, isolate the signal of the other device. pd78e9860a, 78e9861a (2) abnormal operation of other device if the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input ), a signal is output to the dev ice, and this may cause an abnormal operation. to prevent this abnormal operation, isolate the c onnection with the other devic e or set so that the signals input to the ot her device are ignored. figure 17-6. abnormal operation of other device pin connection pin of dedicated flash programmer other device input pin if the signal output by the pd78e9860a, 78e9861a affects another device in the eeprom programming mode, isolate the signals of the other device. pin connection pin of dedicated flash programmer other device input pin if the signal output by the dedicated flash programmer affects another device in the eeprom programming mode, isolate the signals of the other device. pd78e9860a, 78e9861a pd78e9860a, 78e9861a
chapter 17 pd78e9860a, 78e9861a user?s manual u14826ej4v0ud 166 if the reset signal of the dedicated flash programmer is connected to the reset pin c onnected to the reset signal generator on-board, a signal conflict occurs. to prevent this, isolate the connection wit h the reset signal generator. if the reset signal is input from the user system in the eeprom programming mode, a normal programming operation cannot be performed. therefore, do not input other than reset signals from the dedicated flash programmer. figure 17-7. signal conflict (reset pin) reset connection pin of dedicated flash programmer reset signal generator signal conflict output pin the signal output by the reset signal generator and the signal output from the dedicated flash programmer conflict in the eeprom programming mode, so isolate the signal of the reset signal generator. pd78e9860a, 78e9861a when the pd78e9860a and 78e9861a enter the eeprom programmi ng mode, all the pins other than those that communicate with the flash programmer are in the same status as immediately after reset. if the external device does not recogni ze initial statuses such as the output high impedance st atus, therefore, connect the external device to v dd or v ss via a resistor. ? in pd78e9860a when using the on-board clock, connect x1 and x2 as required in the normal operation mode. when using the clock output of the flas h programmer, connect it directly to x1, disconnecting the main resonator on-board, and leave the x2 pin open. ? in pd78e9861a connect cl1 and cl2 as required in the normal operati on mode, and connect the clo ck output of the flash programmer to the p03 pin. to use the power output from t he flash programmer, connect the v dd pin to vdd of the flash programmer, and the v ss pin to gnd of the flash programmer. to use the on-board power supply, ma ke connections that accord with t he normal operation mode. however, because the voltage is monitored by t he flash programmer, be sure to c onnect vdd of the flash programmer.
chapter 17 pd78e9860a, 78e9861a user?s manual u14826ej4v0ud 167 17.1.4 connection of adapter for eeprom writing the following figures show the examples of reco mmended connection when the adapter for eeprom writing is used. figure 17-8. wiring example for eeprom wr iting adapter with pseudo 3-wire (1/2) (a) pd78e9860a si so sck clkout reset vpp reserve/hs pd78e9860a 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd vdd vdd2 (lvdd) vdd (2.7 to 5.5 v) gnd
chapter 17 pd78e9860a, 78e9861a user?s manual u14826ej4v0ud 168 figure 17-8. wiring example for eeprom wr iting adapter with pseudo 3-wire (2/2) (b) pd78e9861a si so sck clkout reset vpp reserve/hs pd78e9861a 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd vdd vdd2 (lvdd) vdd (2.7 to 3.6 v) gnd
user?s manual u14826ej4v0ud 169 chapter 18 mask options the pd789860 and 789861 have the following mask options. p40 to p43 mask options on-chip pull-up resistors can be selected in bit units. <1> specify on-chip pull-up resistors <2> do not specify on-chip pull-up resistors poc circuit mask options the poc circuit can be selected. <1> select poc switching circuit (poc circui t operation control by software is possible) <2> select poc circuit normally operating <3> select poc circuit normally halted oscillation stabilization wait time ( pd789860 only) the oscillation stabilization wait time after the release of stop mode by r eset or the release of reset via the poc circuit can be selected. <1> 2 15 /f x <2> 2 17 /f x
user?s manual u14826ej4v0ud 170 chapter 19 instruction set overview this chapter lists the instruction set of the pd789860, 789861 subseries. for details of the operation and machine language (instruction code) of each instruction, refer to 78k/0s series instructions user?s manual (u11047e) . 19.1 operation 19.1.1 operand identifier s and description methods operands are described in ?operand? colu mn of each instruction in accordanc e with the description method of the instruction operand identifier (refer to the assembler specif ications for details). w hen there are two or more description methods, select one of them. uppercase lette rs and the symbols #, !, $, and [ ] are key words and are described as they are. each symbol has the following meaning. ? #: immediate dat a specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, descr ibe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers, r and rp , either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 19-1. operand identifi ers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even addresses only) addr16 addr5 0000h to ffffh immediate data or labels (only ev en addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark for symbols of special function registers, see table 4-3 special function registers .
chapter 19 instruction set overview user?s manual u14826ej4v0ud 171 19.1.2 description of ?operation? column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: flag indicating non-maskable interrupt servicing in progress ( ): memory contents indicated by addre ss or register contents in parentheses h , l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 19.1.3 description of ?flag? column (blank): unchanged 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is stored
chapter 19 instruction set overview user?s manual u14826ej4v0ud 172 19.2 operation list flag mnemonic operand bytes clocks operation z ac cy r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte a, r note 1 2 4 a r r, a note 1 2 4 r a a, saddr 2 4 a (saddr) saddr, a 2 4 (saddr) a a, sfr 2 4 a sfr sfr, a 2 4 sfr a a, !addr16 3 8 a (addr16) !addr16, a 3 8 (addr16) a psw, #byte 3 6 psw byte a, psw 2 4 a psw psw, a 2 4 psw a a, [de] 1 6 a (de) [de], a 1 6 (de) a a, [hl] 1 6 a (hl) [hl], a 1 6 (hl) a a, [hl + byte] 2 6 a (hl + byte) mov [hl + byte], a 2 6 (hl + byte) a a, x 1 4 a ? x a, r note 2 2 6 a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? sfr a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) xch a, [hl, byte] 2 8 a ? (hl + byte) notes 1. except r = a. 2. except r = a, x. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set overview user?s manual u14826ej4v0ud 173 flag mnemonic operand bytes clocks operation z ac cy rp, #word 3 6 rp word ax, saddrp 2 6 ax (saddrp) saddrp, ax 2 8 (saddrp) ax ax, rp note 1 4 ax rp movw rp, ax note 1 4 rp ax xchw ax, rp note 1 8 ax ? rp a, #byte 2 4 a, cy a + byte saddr, #byte 3 6 (saddr), cy (saddr) + byte a, r 2 4 a, cy a + r a, saddr 2 4 a, cy a + (saddr) a, !addr16 3 8 a, cy a + (addr16) a, [hl] 1 6 a, cy a + (hl) add a, [hl + byte] 2 6 a, cy a + (hl + byte) a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 (saddr), cy (saddr) + byte + cy a, r 2 4 a, cy a + r + cy a, saddr 2 4 a, cy a + (saddr) + cy a, !addr16 3 8 a, cy a + (addr16) + cy a, [hl] 1 6 a, cy a + (hl) + cy addc a, [hl + byte] 2 6 a, cy a + (hl + byte) + cy a, #byte 2 4 a, cy a ? byte saddr, #byte 3 6 (saddr), cy (saddr) ? byte a, r 2 4 a, cy a ? r a, saddr 2 4 a, cy a ? (saddr) a, !addr16 3 8 a, cy a ? (addr16) a, [hl] 1 6 a, cy a ? (hl) sub a, [hl + byte] 2 6 a, cy a ? (hl + byte) note only when rp = bc, de, or hl. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set overview user?s manual u14826ej4v0ud 174 flag mnemonic operand bytes clocks operation z ac cy a, #byte 2 4 a, cy a ? byte ? cy saddr, #byte 3 6 (saddr), cy (saddr) ? byte ? cy a, r 2 4 a, cy a ? r ? cy a, saddr 2 4 a, cy a ? (saddr) ? cy a, !addr16 3 8 a, cy a ? (addr16) ? cy a, [hl] 1 6 a, cy a ? (hl) ? cy subc a, [hl + byte] 2 6 a, cy a ? (hl + byte) ? cy a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) and a, [hl + byte] 2 6 a a (hl + byte) a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) or a, [hl + byte] 2 6 a a (hl + byte) a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) xor a, [hl + byte] 2 6 a a (hl + byte) remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set overview user?s manual u14826ej4v0ud 175 flag mnemonic operand bytes clocks operation z ac cy a, #byte 2 4 a ? byte saddr, #byte 3 6 (saddr) ? byte a, r 2 4 a ? r a, saddr 2 4 a ? (saddr) a, !addr16 3 8 a ? (addr16) a, [hl] 1 6 a ? (hl) cmp a, [hl + byte] 2 6 a ? (hl + byte) addw ax, #word 3 6 ax, cy ax + word subw ax, #word 3 6 ax, cy ax ? word cmpw ax, #word 3 6 ax ? word r 2 4 r r + 1 inc saddr 2 4 (saddr) (saddr) + 1 r 2 4 r r ? 1 dec saddr 2 4 (saddr) (saddr) ? 1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ? 1 ror a, 1 1 2 (cy, a 7 a 0 , a m ? 1 a m ) 1 rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ? 1 a m ) 1 rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 3 6 psw.bit 1 set1 [hl].bit 2 10 (hl).bit 1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 3 6 psw.bit 0 clr1 [hl].bit 2 10 (hl).bit 0 set1 cy 1 2 cy 1 1 clr1 cy 1 2 cy 0 0 not1 cy 1 2 cy cy remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set overview user?s manual u14826ej4v0ud 176 flag mnemonic operand bytes clocks operation z ac cy call !addr16 3 6 (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callt [addr5] 1 8 (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 ret 1 6 pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 8 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3, nmis 0 r r r psw 1 2 (sp ? 1) psw, sp sp ? 1 push rp 1 4 (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 4 psw (sp), sp sp + 1 r r r pop rp 1 6 rp h (sp + 1), rp l (sp), sp sp + 2 sp, ax 2 8 sp ax movw ax, sp 2 6 ax sp !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 br ax 1 6 pc h a, pc l x bc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 0 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 bt psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 1 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 bf psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 0 b, $addr16 2 6 b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ? 1, then pc pc + 2 + jdisp8 if c 0 dbnz saddr, $addr16 3 8 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 nop 1 2 no operation ei 3 6 ie 1 (enable interrupt) di 3 6 ie 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set overview user?s manual u14826ej4v0ud 177 19.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr ! addr16 psw [de] [hl] [hl + byte] $addr16 1 none a add addc sub subc and or xor cmp mov note xch note add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov [hl + byte] mov note except r = a.
chapter 19 instruction set overview user?s manual u14826ej4v0ud 178 (2) 16-bit instructions movw, xchw, addw, subw, cmpw , push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when rp = bc, de, or hl. (3) bit manipulation instructions set1, clr1, not1, bt, bf 2nd operand 1st operand $addr16 none a.bit bt bf set1 clr1 sfr.bit bt bf set1 clr1 saddr.bit bt bf set1 clr1 psw.bit bt bf set1 clr1 [hl].bit set1 clr1 cy set1 clr1 not1
chapter 19 instruction set overview user?s manual u14826ej4v0ud 179 (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, reti, nop, ei, di, halt, stop
user?s manual u14826ej4v0ud 180 chapter 20 electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd ?0.3 to +6.5 v supply voltage v pp pd78e9860a, 78e9861a only, note ?0.3 to +10.5 v input voltage v i ?0.3 to v dd + 0.3 v output voltage v o ?0.3 to v dd + 0.3 v per pin ?10 ma output current, high i oh total of all pins ?30 ma per pin 30 ma output current, low i ol total of all pins 80 ma operating ambient temperature t a ?40 to +85 c storage temperature t stg ?40 to +125 c note make sure that the following conditions of the v pp voltage application timing are satisfied when the eeprom (program memory) is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit va lue (1.8 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit va lue (1.8 v) of the operating voltage range of v dd (see b in the figure below). 1.8 v v dd 0 v 0 v v pp 1.8 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum rating are rated values at which the product is on the verge of suffering physical damage , and therefore the product must be used under conditions the ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 20 electrical specifications user?s manual u14826ej4v0ud 181 system clock oscilla tor characteristics ceramic or crystal oscillation ( pd789860, 78e9860a) (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz ceramic resonator x1 x2 v ss oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms oscillation frequency (f x ) note 1 1.0 5.0 mhz crystal resonator x1 x2 v ss oscillation stabilization time note 2 30 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz external clock x1 x2 x1 input high-/low- level width(t xh ,t xl ) 85 500 ns notes. 1. indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. caution when using a ceramic or cr ystal oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross with other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the o scillator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant of the pd78e9860a, customers are required to either evaluate the oscillation t hemselves or apply to the resonat or manufacturer for evaluation.
chapter 20 electrical specifications user's manual u14826ej4v0ud 182 recommended oscillator constant ceramic resonator (t a = ?40 to +85 c) (mask rom version) recommended circuit constant (pf) oscillation voltage range (v dd ) manufacturer part number frequency (mhz) c1 c2 min. max. remark csbla1m00j58-b0 100 100 2.1 5.5 csbfb1m00j58-b0 1.0 100 100 2.1 5.5 cstls2m00g56-b0 ? ? 1.8 5.5 on-chip capacitor cstcc2m00g56-b0 2.0 ? ? 1.8 5.5 on-chip capacitor cstls4m00g53-b0 ? ? 1.8 5.5 on-chip capacitor cstcr4m00g53-r0 4.0 ? ? 1.8 5.5 on-chip capacitor cstls4m19g53-b0 ? ? 1.8 5.5 on-chip capacitor cstcr4m19g53-r0 4.19 ? ? 1.8 5.5 on-chip capacitor cstls4m91g53-b0 ? ? 1.9 5.5 on-chip capacitor cstcr4m91g53-r0 4.91 ? ? 1.8 5.5 on-chip capacitor cstls5m00g53-b0 ? ? 1.9 5.5 on-chip capacitor murata mfg. co., ltd. cstcr5m00g53-r0 5.0 ? ? 1.8 5.5 on-chip capacitor caution the oscillator constant a nd oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for app lications requiring oscillation frequency precision, the oscillation must be adjusted on the implem entation circuit. for details, please contact directly the manufactur er of the resonator you will use.
chapter 20 electrical specifications user?s manual u14826ej4v0ud 183 rc oscillation ( pd789861, 78e9861a) (t a = ?40 to +85 c, v dd = 1.8 to 3.6 v) resonator recommended circuit parameter conditions min. typ. max. unit rc oscillator cl2 cl1 oscillation frequency (f cc ) notes 1,2 v dd = oscillation voltage range 0.85 1.15 mhz cl1 input frequency (f cc ) note 1 1.0 5.0 mhz external clock cl1 cl2 cl1 input high-/low- level width (t xh ,t xl ) 85 500 ns notes 1. indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. 2. variations due to external resistance and external capacitanc e are not included. caution when using an rc oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross with other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the o scillator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator.
chapter 20 electrical specifications user's manual u14826ej4v0ud 184 dc characteristics ( pd789860, 78e9860a) (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit per pin 3 ma output current, low i ol all pins 7.5 ma per pin ?0.75 ma output current, high i oh all pins ?7.5 ma 2.7 v dd 5.5 v 0.7v dd v dd v v ih1 p00 to p07 1.8 v dd < 2.7 v 0.9v dd v dd v 2.7 v dd 5.5 v 0.8v dd v dd v v ih2 reset, p20, p21, p40 to p43 1.8 v dd < 2.7 v 0.9v dd v dd v input voltage, high v ih3 x1, x2 v dd ? 0.1 v dd v 2.7 v dd 5.5 v 0 0.3v dd v v il1 p00 to p07 1.8 v dd < 2.7 v 0 0.1v dd v 2.7 v dd 5.5 v 0 0.2v dd v v il2 reset, p20, p21, p40 to p43 1.8 v dd < 2.7 v 0 0.1v dd v input voltage, low v il3 x1, x2 0 0.1 v v oh1 i oh = ?100 a v dd ? 0.5 v output voltage, high v oh2 p00 to p07, p20, p21 i oh = ?500 a v dd ? 0.7 v v ol1 i ol = 400 a 0.5 v output voltage, low v ol2 p00 to p07, p20, p21 i ol = 2 ma 0.7 v i lih1 pins other than x1, x2 3 a input leakage current, high i lih2 v i = v dd x1, x2 20 a i lil1 pins other than x1, x2 ?3 a input leakage current, low i lil2 v i = 0 v x1, x2 ?20 a output leakage current, high i loh v o = v dd p00 to p07, p20, p21 3 a output leakage current, low i lol v o = 0 v p00 to p07, p20, p21 ?3 a mask-option pull-up resistor note r v in = 0 v p40 to p43 50 100 200 k ? note pd789860 only. remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 20 electrical specifications user?s manual u14826ej4v0ud 185 dc characteristics ( pd789861, 78e9861a) (t a = ?40 to +85 c, v dd = 1.8 to 3.6 v) parameter symbol conditions min. typ. max. unit per pin 2 ma output current, low i ol all pins 5.0 ma per pin ?0.5 ma output current, high i oh all pins ?5.0 ma 2.7 v dd 3.6 v 0.7v dd v dd v v ih1 p00 to p07 1.8 v dd < 2.7 v 0.9v dd v dd v 2.7 v dd 3.6 v 0.8v dd v dd v v ih2 reset, p20, p21, p40 to p43 1.8 v dd < 2.7 v 0.9v dd v dd v input voltage, high v ih3 cl1, cl2 v dd ? 0.1 v dd v 2.7 v dd 3.6 v 0 0.3v dd v v il1 p00 to p07 1.8 v dd < 2.7 v 0 0.1v dd v 2.7 v dd 3.6 v 0 0.2v dd v v il2 reset, p20, p21, p40 to p43 1.8 v dd < 2.7 v 0 0.1v dd v input voltage, low v il3 cl1, cl2 0 0.1 v v oh1 i oh = ?100 a v dd ? 0.5 v output voltage, high v oh2 p00 to p07, p20, p21 i oh = ?500 a v dd ? 0.7 v v ol1 i ol = 400 a 0.5 v output voltage, low v ol2 p00 to p07, p20, p21 i ol = 2 ma 0.7 v i lih1 pins other than cl1, cl2 3 a input leakage current, high i lih2 v i = v dd cl1, cl2 20 a i lil1 pins other than cl1, cl2 ?3 a input leakage current, low i lil2 v i = 0 v cl1, cl2 ?20 a output leakage current, high i loh v o = v dd p00 to p07, p20, p21 3 a output leakage current, low i lol v o = 0 v p00 to p07, p20, p21 ?3 a mask-option pull-up resistor note r v in = 0 v p40 to p43 50 100 200 k ? note pd789861 only. remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 20 electrical specifications user's manual u14826ej4v0ud 186 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v ( pd789860)) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% 1.1 2.2 ma i dd1 5.0 mhz crystal oscillation operating mode (eeprom halted) c 1 = c 2 = 22 pf v dd = 3.0 v 10% 0.5 1.0 ma v dd = 5.0 v 10% 1.5 3.0 ma i dd2 5.0 mhz crystal oscillation operating mode (eeprom halted) c 1 = c 2 = 22 pf v dd = 3.0 v 10% 0.8 1.6 ma v dd = 5.0 v 10% 0.6 1.2 ma i dd3 5.0 mhz crystal oscillation halt mode (eeprom halted) c 1 = c 2 = 22 pf v dd = 3.0 v 10% 0.3 0.6 ma v dd = 5.0 v t a = ? 40 to +85 c 1.2 4.0 a v dd = 3.0 v 10% t a = ? 40 to +85 c 1.0 2.5 a v dd = 5.0 v t a = ? 20 to +75 c 1.2 3.0 a i dd4 stop mode (poc operating) v dd = 3.0 v 10% t a = ? 20 to +75 c 1.0 1.5 a v dd = 5.0 v t a = ? 40 to +85 c 3.0 a v dd = 3.0 v 10% t a = ? 40 to +85 c 0.7 a power supply current note ceramic/crystal oscillation i dd5 stop mode (poc operation halted) v dd = 5.0 v t a = 25 c 0.9 a note port current (including current flowing in on-chip pull-up resistors) is not included. remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 20 electrical specifications user?s manual u14826ej4v0ud 187 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 3.6 v ( pd789861)) parameter symbol conditions min. typ. max. unit i dd1 1.0 mhz rc oscillation operating mode (eeprom halted) r = 24 k ? , c = 30 pf v dd = 3.0 v 10% 0.4 0.8 ma i dd2 1.0 mhz rc oscillation operating mode (eeprom halted) r = 24 k ? , c = 30 pf v dd = 3.0 v 10% 0.5 1.0 ma i dd3 1.0 mhz rc oscillation halt mode (eeprom halted) r = 24 k ? , c = 30 pf v dd = 3.0 v 10% 0.3 0.6 ma v dd = 3.0 v 10% t a = ? 40 to +85 c 1.0 2.5 a i dd4 stop mode (poc operating) v dd = 3.0 v 10% t a = ?20 to +75 c 1.0 1.5 a power supply current note rc oscillation i dd5 stop mode (poc operation halted) v dd = 3.0 v 10% t a = ?40 to +85 c 0.7 a note port current (including current flowing in on-chip pull-up resistors) is not included. remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 20 electrical specifications user's manual u14826ej4v0ud 188 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v ( pd78e9860a), v dd = 1.8 to 3.6 v ( pd78e9861a)) parameter symbol conditions min. typ. max. unit i dd1 5.0 mhz crystal oscillation operating mode (eeprom halted) c 1 = c 2 = 22 pf v dd = 3.0 v 10% 2.5 5.0 ma i dd2 5.0 mhz crystal oscillation operating mode (eeprom halted) c 1 = c 2 = 22 pf v dd = 3.0 v 10% 3.0 6.0 ma i dd3 4.19 mhz crystal oscillation halt mode (eeprom halted) c 1 = c 2 = 22 pf v dd = 3.0 v 10% 1.6 3.2 ma v dd = 5.0 v t a = ? 40 to +85 c 1.2 4.0 a v dd = 3.0 v 10% t a = ? 40 to +85 c 1.0 2.5 a v dd = 5.0 v t a = ? 20 to +75 c 3.0 a i dd4 stop mode (poc operating) v dd = 3.0 v 10% t a = ? 20 to +75 c 1.0 2.0 a v dd = 5.0 v t a = ? 40 to +85 c 3.0 a v dd = 3.0 v 10% t a = ? 40 to +85 c 1.5 a power supply current note ceramic/crystal oscillation: pd78e9860a i dd5 stop mode (poc operation halted) v dd = 5.0 v t a = 25 c 0.9 a i dd1 1.0 mhz rc oscillation operating mode (eeprom halted) r = 24 k ? , c = 30 pf v dd = 3.0 v 10% 0.8 1.6 ma i dd2 1.0 mhz rc oscillation operating mode (eeprom halted) r = 24 k ? , c = 30 pf v dd = 3.0 v 10% 1.0 2.0 ma i dd3 1.0 mhz rc oscillation halt mode (eeprom halted) r = 24 k ? , c = 30 pf v dd = 3.0 v 10% 0.7 1.4 ma v dd = 3.0 v 10% t a = ? 40 to +85 c 1.0 2.5 a i dd4 stop mode (poc operating) v dd = 3.0 v 10% t a = ?20 to +75 c 1.0 2.0 a power supply current note rc oscillation: pd78e9861a i dd5 stop mode (poc operation halted) v dd = 3.0 v 10% 1.5 a note port current (including current flowing in on-chip pull-up resistors) is not included. remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 20 electrical specifications user?s manual u14826ej4v0ud 189 ac characteristics (1) basic operation (a) pd789860, 78e9860a (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit 2.7 v dd 5.5 v 0.4 8 s cycle time (minimum instruction execution time) ceramic/crystal oscillation t cy 1.8 v dd < 2.7 v 1.6 8 s 2.7 v dd 5.5 v 0 4.0 mhz tmi input input frequency f ti 1.8 v dd < 2.7 v 0 500 khz 2.7 v dd 5.5 v 0.1 s tmi high-/low-level width t tih , t til 1.8 v dd < 2.7 v 1.0 s key return input pin low-level width t kril kr10 to kr13 10 s reset low-level width t rsl 10 s t cy vs. v dd (system clock: ceramic/crystal oscillation) 123456 0.1 0.4 0.5 1.0 2.0 10 20 60 supply voltage v dd (v) cycle time t cy [ s] guaranteed operation range
chapter 20 electrical specifications user's manual u14826ej4v0ud 190 (b) pd789861, 78e9861a (t a = ?40 to +85 c, v dd = 1.8 to 3.6 v) parameter symbol conditions min. typ. max. unit 2.7 v dd 3.6 v 0.4 9.42 s cycle time (minimum instruction execution time) rc oscillation t cy 1.8 v dd < 2.7 v 1.6 9.42 s 2.7 v dd 3.6 v 0 4.0 mhz tmi input input frequency f ti 1.8 v dd < 2.7 v 0 500 khz 2.7 v dd 3.6 v 0.1 s tmi high-/low-level width t tih , t til 1.8 v dd < 2.7 v 1.0 s key return input pin low-level width t kril kr10 to kr13 10 s reset low-level width t rsl 10 s t cy vs. v dd (system clock: rc oscillation) supply voltage v dd (v) 123456 0.1 0.4 1.0 2.0 10 20 60 cycle time t cy [ s] guaranteed operation range (2) rc frequency oscillation characteristics (t a = ?40 to +85 c, v dd = 1.8 to 3.6 v) parameter symbol conditions min. typ. max. unit oscillation frequency note f cc r = 24 k ? , c = 30 pf 0.85 1.00 1.15 mhz note variations due to external resistance and external capacitanc e are not included.
chapter 20 electrical specifications user?s manual u14826ej4v0ud 191 ac timing measurement points (excluding x1, cl1 input) 0.8v dd 0.2v dd points of measurement 0.8v dd 0.2v dd clock timing 1/f clk t xl t xh x1 (cl1) input v ih3 (min.) v il3 (max.) remark f clk : f x or f cc tmi timing tmi t til t tih 1/f ti key return input timing kr10 to kr13 t kril reset input timing reset t rsl
chapter 20 electrical specifications user's manual u14826ej4v0ud 192 power-on-clear circuit characteristics (1) poc (a) dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v ( pd789860, 78e9860a), v dd = 1.8 to 3.6 v ( pd789861, 78e9861a)) parameter symbol conditions min. typ. max. unit detection voltage v poc response time note 1 : 2 ms 1.8 note 2 1.9 note 2 2.0 v notes 1. time from detecting voltage until output reverses and time until stabl e operation after transition from halted state to operating state. 2. note that the poc detection vo ltage may be lower than the operati ng voltage range of these products. (b) ac characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit t pth1 poc selector used v dd : 0 1.8 v 0.01 100 ms t pth2 poc normal operation v dd : 0 1.8 v 0.01 100 ms power rise time t pth3 poc normal operation v dd : 0 1.8 v t a = +25 c 10 s (2) lvi (a) dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v ( pd789860, 78e9860a), v dd = 1.8 to 3.6 v ( pd789861, 78e9861a)) parameter symbol conditions min. typ. max. unit lvi7 detection voltage v lvi7 response time note 1 : 2 ms 2.4 2.6 2.8 v lvi6 detection voltage v lvi6 response time note 1 : 2 ms note 2 v lvi5 detection voltage v lvi5 response time note 1 : 2 ms note 2 v lvi4 detection voltage v lvi4 response time note 1 : 2 ms note 2 v lvi3 detection voltage v lvi3 response time note 1 : 2 ms note 2 v lvi2 detection voltage v lvi2 response time note 1 : 2 ms note 2 v lvi1 detection voltage v lvi1 response time note 1 : 2 ms note 2 v lvi0 detection voltage v lvi0 response time note 1 : 2 ms note 3 2.0 2.2 v notes 1. time from detecting voltage until out put reverses and time until stable operation after transition from halted state to operating state 2. relative relationship: v lvi7 > v lvi6 > v lvi5 > v lvi4 > v lvi3 > v lvi2 > v lvi1 > v lvi0 3. v poc < v lvi0
chapter 20 electrical specifications user?s manual u14826ej4v0ud 193 eeprom characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v ( pd789860, 78e9860a), v dd = 1.8 to 3.6 v ( pd789861, 78e9861a)) parameter symbol conditions min. typ. max. unit write time note 1 3.3 6.6 ms 32 bytes per byte 10 10,000 times number of overwrites 4 kb note 2 per byte 100 times notes 1. write time = t 145 (t = time of 1 clock cycle selected by ewcs100 to ewcs102) 2. pd78e9860a, 78e9861a only. data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit pd789860, 78e9860a 1.8 5.5 v data retention power supply voltage v dddr pd789861, 78e9861a 1.8 3.6 v release signal set time t srel stop release by reset pin 10 s data retention timing v dd data retention mode stop mode halt mode internal reset operation operation mode t srel t wait stop instruction execution v dddr reset v dd data retention mode stop mode halt mode operation mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
chapter 20 electrical specifications user's manual u14826ej4v0ud 194 oscillation stabilization wait time (a) ceramic/crystal oscillator (t a = ? 40 to 85 c, v dd = 1.8 to 5.5 v) ( pd789860, 78e9860a) parameter symbol conditions min. typ. max. unit stop release by reset or reset release by poc note 2 s oscillation wait time note 1 t wait release by interrupt note 3 s notes 1. time required to stabilize oscillation after a reset or stop mode release. 2. this is fixed to 2 15 /f x in the pd78e9860a. in the pd789860, 2 15 /f x or 2 17 /f x can be selected by a mask option. 3. 2 12 /f x , 2 15 /f x , or 2 17 /f x can be selected using bits 0 to 2 of t he oscillation stabilization time selection register (osts0 to osts2). (b) rc oscillation (t a = ? 40 to +85 c, v dd = 1.8 to 3.6 v) ( pd789861, 78e9861a) parameter symbol conditions min. typ. max. unit stop release by reset or reset release by poc 2 7 /f cc s oscillation wait time note t wait release by interrupt 2 7 /f cc s note time required to stabilize oscillation after a reset or stop mode release.
user?s manual u14826ej4v0ud 195 chapter 21 example of rc osci llation frequency characteristics (reference values) f cc vs. v dd (rc oscillation: pd789861, r = 24 k ? , c = 30 pf) (t a = 25?c) 1.10 1.05 1.0 0.95 0.90 supply voltage v dd [v] 1.5 2.0 3.0 4.0 sample a sample b sample c cl2 cl1 24 k ? 30 pf system clock frequency f cc [mhz]
user's manual u14826ej4v0ud 196 chapter 22 package drawing ns c dm m p l u t g f e b k j detail of lead end s 20 11 110 a h i item b c i l m n 20-pin plastic ssop (7.62 mm (300)) a k d e f g h j p t millimeters 0.65 (t.p.) 0.475 max. 0.13 0.5 6.1 0.2 0.10 6.65 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 ? 0.07 1.0 0.2 3 + 5 ? 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. s20mc-65-5a4-2
user?s manual u14826ej4v0ud 197 chapter 23 recommended soldering conditions the pd789860, 789861, 78e9860a, and 78e9861a should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http ://www.necel.com/pkg/en/mount/index/html) table 23-1. surface mounting ty pe soldering conditions (1/2) pd789860mc- -5a4: 20-pin plastic ssop (7.62 mm (300)) pd789861mc- -5a4: 20-pin plastic ssop (7.62 mm (300)) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: three times or less ir35-00-3 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: three times or less vp15-00-3 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature) ws60-00-1 partial heating pin temperature: 300 c max. time: 3 seconds max. (per pin row) ? caution do not use different soldering me thod together (except for partial heating).
chapter 23 recommended soldering conditions user's manual u14826ej4v0ud 198 table 23-1. surface mounting ty pe soldering conditions (2/2) pd78e9860amc-5a4: 20-pin plastic ssop (7.62 mm (300)) pd78e9861amc-5a4: 20-pin plastic ssop (7.62 mm (300)) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir35-103-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) vp15-103-2 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ws60-103-1 partial heating pin temperature: 300 c max. time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering me thod together (except for partial heating).
user?s manual u14826ej4v0ud 199 appendix a development tools the following development tools are avail able for development of systems using the pd789860, 789861 subseries. figure a-1 shows development tools. ? compatibility with pc98-nx series unless stated otherwise, products wh ich are supported by ibm pc/at tm and compatibles can also be used with the pc98-nx series. when using the pc98-nx series, t herefore, refer to the explanations for ibm pc/at and compatibles. ? windows unless stated otherwise, ?windows? refe rs to the following operating systems. ? windows 3.1 ? windows 95, 98, 2000 ? windows nt tm ver. 4.0
appendix a development tools user?s manual u14826ej4v0ud 200 figure a-1. development tools language processing software ? assembler package ? c compiler package ? device file ? c library source file note 1 debugging software ? integrated debugger ? system simulator host machine (pc or ews) interface adapter in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory writing adapter flash memory power supply unit ? software package control software ? project manager (windows version only) note 2 software package flash memory writing environment notes 1. a c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is used only in the windows environment.
appendix a development tools user?s manual u14826ej4v0ud 201 a.1 software package this is a package that bundles the software tool s required for development of the 78k/0s series. the following tools are included. ra78k0s, cc78k0s, id78k0s-ns, sm78k0s, and device files sp78k0s software package part number: s sp78k0s remark in the part number differs depending on the operating system to be used. s sp78k0s host machine os supply medium ab17 japanese windows bb17 pc-9800 series, ibm pc/at and compatibles english windows cd-rom a.2 language processing software program that converts program written in mnemonic into objec t code that can be executed by microcontroller. in addition, automatic functions to generate symbol table and optimize branch instructions are also provided. used in combination wi th optional device file (df789861). the assembler package is a dos-based app lication but may be used under the windows environment by using projec t manager of windows (included in the assembler package). ra78k0s assembler package part number: s ra78k0s program that converts program written in c language into object codes that can be executed by microcontroller. used in combination with optional assemble r package (ra78k0s) and device file (df789861). the c compiler package is a dos-based app lication but may be used under the windows environment by using projec t manager of windows (included in the assembler package). cc78k0s c library package part number: s cc78k0s file containing the informat ion inherent to the device. used in combination with other optional tools (ra78k0s, cc78k0s, id78k0s-ns, or sm78k0s). df789861 note 1 device file part number: s df789861 source file of functions constituting obj ect library included in c compiler package. necessary for changing object library included in c compiler package according to customer?s specifications. since this is the source f ile, its working environment does not depend on any particular operating system. cc78k0s-l note 2 c library source file part number: s cc78k0s-l notes 1. df789861 is a common file that can be used with ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s. 2. cc78k0s-l is not included in the software package (sp78k0s).
appendix a development tools user?s manual u14826ej4v0ud 202 remark in the part number differs depending on the hos t machine and operating system to be used. s ra78k0s s cc78k0s host machine os supply media ab13 japanese windows bb13 english windows 3.5? 2hd fd ab17 japanese windows bb17 pc-9800 series, ibm pc/at and compatibles english windows 3p17 hp9000 series 700 tm hp-ux tm (rel.10.10) 3k17 sparcstation tm sunos tm (rel.4.1.4), solaris tm (rel.2.5.1) cd-rom s df789861 s cc78k0s-l host machine os supply media ab13 japanese windows bb13 pc-9800 series, ibm pc/at and compatibles english windows 3.5? 2hd fd 3p16 hp9000 series 700 hp-ux (rel.10.10) dat 3k13 3.5? 2hd fd 3k15 sparcstation sunos (rel.4.1.4), solaris (rel.2.5.1) 1/4? cgmt a.3 control software project manager this is control so ftware designed so that the user program can be efficiently developed in the windows environment. with this software, a series of user program development operations, including starting the editor, build, and starting the debugger, can be executed on the project manager. the project manager is included in the asse mbler package (ra78k0s). it can be used only in the windows environment. a.4 eeprom (program memory) writing tools flashpro iii (fl-pr3, pg-fp3) flashpro iv (fl-pr4, pg-fp4) flash programmer flash programmer dedicated to the microcont rollers incorporating a flash memory (eeprom) fa-20mc flash memory (eeprom) writing adapter flash memory (eeprom) writing adapter. used in connection with flashpro iii or flashpro iv. remark fl-pr3, fl-pr4, and fa-20mc are products of naito densei machida mfg. co., ltd. for further information, contact: naito densei machida mfg. co., ltd. (tel +81-45-475-4191)
appendix a development tools user?s manual u14826ej4v0ud 203 a.5 debugging tools (hardware) ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging hardware and software of application system using 78k/0s series. supports integrated debugger (id78k0s-n s). used in combination with ac adapter, emulation probe, and interface adapter for connecting the host machine. ie-78k0s-ns-a in-circuit emulator this in-circuit emulator has a coverage function in addition to the functions of the ie-78k0s- ns, and enhanced debugging functions such as an enhanced tracer function and timer function. ie-70000-mc-ps-b ac adapter adapter for supplying power from 100 to 240 vac outlet. ie-70000-98-if-c interface adapter adapter required when using a pc-9800 series (e xcept notebook type) as the host machine (c bus supported). ie-70000-cd-if-a pc card interface pc card and interface cable required when us ing a notebook type pc as the host machine (pcmcia socket supported). ie-70000-pc-if-c interface adapter adapter required when using ibm pc/at and co mpatibles as the host machine (isa bus supported). ie-70000-pci-if-a interface adapter adapter required when using a personal computer incorporating the pci bus is used as the host machine. ie-789860-ns-em1 emulation board emulation board for emulating the peripher al hardware inherent to the device. used in combination with in-circuit emulator. np-20gs emulation probe board for connecting in-circuit emulator and target system. used in combination with ev-9500gs-20. ev-9500gs-20 conversion adapter conversion adapter for connecting target system board for mounting 20-pin plastic ssop and np-20gs. remark np-20gs is a product of naito d ensei machida mfg. co., ltd. for further information, contact: naito dens ei machida mfg. co., ltd. (tel +81-45-475-4191)
appendix a development tools user?s manual u14826ej4v0ud 204 a.6 debugging tools (software) this debugger supports the in-cir cuit emulators for the 78k/0s series, ie-78k0s-ns and ie- 78k0s-ns-a. id78k0s-ns is windows-based software. this debugger has enhanced debugging f unctions supporting c language. by using its window integration function that associates the sour ce program, disassemble display, and memory display with trace results, the trace result s can be displayed corresponding to the source program. it is used with a device file (df789861) (sold separately). id78k0s-ns integrated debugger part number: s id78k0s-ns this is a system simulator for the 78k/0s series. sm78k0s is windows-based software. this simulator can execute c- source-level or assembler-lev el debugging while simulating the operations of the target system on the host machine. by using sm78k0s, the logic and performance of the application can be verified independently of hardware development. therefore, t he development efficiency can be enhanced and the software quality can be improved. this simulator is used with a devic e file (df789861) (sold separately). sm78k0s system simulator part number: s sm78k0s this is a file that has dev ice-specific information. it is used with the ra78k0s, cc78k0s, id78k 0s-ns, and sm78k0s (all sold separately). df789861 note device file part number: s df789861 note df789861 is a common file that can be used with the ra78k0s, cc 78k0s, id78k0s-ns, and sm78k0s. remark in the part number differs depending on the operat ing system to be used and the supply medium. s id78k0s-ns s sm78k0s host machine os supply medium ab13 japanese windows bb13 english windows 3.5? 2hd fd ab17 japanese windows bb17 pc-9800 series, ibm pc/at and compatibles english windows cd-rom
user?s manual u14826ej4v0ud 205 appendix b notes on target system design the following show the conditions when connecting t he emulation probe to t he conversion connector and conversion socket. follow the configuration below and c onsider the shape of parts to be mounted on the target system when designing a system. figure b-1. connection condition of target in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a cn1 185 mm 45 mm 10 mm 43 mm 100 mm 30 mm target system 15 mm 1 pin emulation board ie-789860-ns-em1 emulation board ie-789860-ns-em1 emulation probe np-20gs emulation probe np-20gs conversion connector: ev-9500gs-20 target system conversion socket: ev-9500gs-20 remark the np-20gs is a product made by na ito densei machida mfg. co., ltd.
user?s manual u14826ej4v0ud 206 appendix c register index c.1 register name index (in alphabetical order) [b] bit sequential buffer 10 data regist ers l, h (bsf rl10, bsf rh10)................................................................ .............132 bit sequential buffer output cont rol register 10 (bsf c10) ...................................................................... .....................133 [c] carrier generator output cont rol register 40 (t ca40) ........................................................................... .........................91 [e] eeprom write control r egister 10 (eewc 10) ...................................................................................... ........................58 8-bit compare regi ster 30 (cr30) ............................................................................................... ...................................87 8-bit compare regi ster 40 (cr40) ............................................................................................... ...................................87 8-bit compare regi ster h40 (crh 40)............................................................................................. ................................87 8-bit timer count er 30 (t m30).................................................................................................. ......................................87 8-bit timer count er 40 (t m40).................................................................................................. ......................................87 8-bit timer mode contro l register 30 (tmc 30)................................................................................... .............................89 8-bit timer mode contro l register 40 (tmc 40)................................................................................... .............................90 [i] interrupt mask flag register 0 (mk0) ........................................................................................... .................................140 interrupt request flag register 0 (if0)........................................................................................ ...................................139 [l] low-voltage detection level sele ction register 1 (lvi s1) ....................................................................... ......................127 low-voltage detection r egister 1 (lvif1)....................................................................................... ..............................127 [o] oscillation stabilization time selection regi ster (osts) ....................................................................... ........................149 [p] port 0 (p0).................................................................................................................... .................................................64 port 2 (p2).................................................................................................................... .................................................65 port 4 (p4).................................................................................................................... .................................................66 port mode regist er 0 (p m0) ..................................................................................................... ......................................67 port mode regist er 2 (p m2) ..................................................................................................... ........................67, 92, 133 power-on-clear regi ster 1 (p ocf1).............................................................................................. ...............................126 processor clock cont rol regist er (pcc) ......................................................................................... ..........................70, 77 [t] timer clock selection register 2 (tc l2)........................................................................................ ...............................120 [w] watchdog timer mode r egister (wdtm)............................................................................................ ..........................121
appendix c register index user?s manual u14826ej4v0ud 207 c.2 register symbol ind ex (in alphabetical order) [b] bsfc10: bit sequential buffer out put control r egister 10 ....................................................................... .................133 bsfrl10, bsfrh10: bit sequential buffer 10 data regist ers l, h .......................................................................... ...................132 [c] cr30: 8-bit compar e regist er 30 ................................................................................................ ..........................87 cr40: 8-bit compar e regist er 40 ................................................................................................ ..........................87 crh40: 8-bit compar e register h40.............................................................................................. ..........................87 [e] eewc10: eeprom write c ontrol regi ster 10....................................................................................... ......................58 [i] if0: interrupt reques t flag regi ster 0 ......................................................................................... ......................139 [l] lvif1: low-voltage det ection regi ster 1........................................................................................ ......................127 lvis1: low-voltage detection le vel selection register 1 ........................................................................ ..............127 [m] mk0: interrupt mask flag regist er 0............................................................................................ .......................140 [o] osts: oscillation stabilization time selecti on regi ster ........................................................................ ................149 [p] p0: port 0..................................................................................................................... ....................................64 p2: port 2..................................................................................................................... ....................................65 p4: port 4..................................................................................................................... ....................................66 pcc: processor clo ck control regist er .......................................................................................... ................70, 77 pm0: port mode register 0...................................................................................................... ............................67 pm2: port mode register 2...................................................................................................... .............. 67, 92, 133 pocf1: power-on-cl ear regist er 1 ............................................................................................... .........................126 [t] tca40: carrier generator out put control r egister 40 ............................................................................ ..................91 tcl2: timer clock sele ction regi ster 2 ......................................................................................... ......................120 tm30: 8-bit time r counter 30 ................................................................................................... .............................87 tm40: 8-bit time r counter 40 ................................................................................................... .............................87 tmc30: 8-bit timer mode control regi ster 30.................................................................................... .......................89 tmc40: 8-bit timer mode control regi ster 40.................................................................................... .......................90 [w] wdtm: watchdog time r mode r egister ............................................................................................. ...................121
user?s manual u14826ej4v0ud 208 appendix d revision history revisions up to this edition are shown below. the ?appli ed to? column indicates the chapter in each edition to which the revision was applied. (1/2) edition description applied to change of pd789860, 789861 subseries status from under development to development completed throughout modification of inttmn0 timing in figure 9-12 timing of interval timer operation with 8-bit resolution (when crn0 changes from n to m (n > m)) chapter 9 8-bit timer modification of figure 11-2 block diagram of low-voltage detection circuit modification of internal reset signal timing in figure 11-8 timing of internal reset signal generation in poc switching circuit revision of description in 11.4.2 operation of low-voltage detection (lvi) circuit chapter 11 power-on- clear circuit modification of caution in 14.4.1 non-maskable interrupt request acknowledgement operation modification of figure 14-7 acknowledgement of non-maskable interrupt request chapter 14 interrupt functions addition of note 1 for pins used in table 17-2 communication mode chapter 17 pd78e9860, 78e9861 2nd addition of ie-78k0s-ns-a, ie -70000-pci-if-a, and ev-9500gs-20 in a.3.1 hardware appendix a development tools change of pd78e9860 and 78e9861 to pd78e9860a and 78e9861a change of supply voltage of pd789860 and 78e9860a throughout modification of related documents to latest version introduction update of series lineup chart to latest version chapter 1 general ( pd789860 subseries) chapter 2 general ( pd789861 subseries) change of processing of v pp pin in 3.2.9 v pp ( pd78e9860a and 78e9861a only) and table 3-1 types of pin i/o circuits and recommended connection of unused pins chapter 3 pin functions addition of caution to 13.1 key return circuit function modification of figure 13-1 block diagram of key return circuit chapter 13 key return circuit modification of figure of releasing stop mode in figure 15-1 format of oscillation stabilization time selection register chapter 15 standby function total revision of descriptions on eeprom (program memory) chapter 17 pd78e9860a, 78e9861a 3rd total revision of descripti ons of development tools deletion of embedded software appendix a development tools
appendix d revision history user?s manual u14826ej4v0ud 209 (2/2) edition description applied to ? update of 1.5 78k/0s series lineup and 2.5 78k/0s series lineup to latest version chapter 1 general ( pd789860 subseries) chapter 2 general ( pd789861 subseries) ? modification of description of 3.2.9 v pp ( pd78e9860a, 78e9861a only) chapter 3 pin functions ? addition of description of timer input of p21 to 9.3 (4) port mode register 2 (pm2) chapter 9 8-bit timers 30 and 40 ? modification of figure 11-1 block diagram of power-on-clear circuit and figure 11-2 block diagram of low-voltage detection circuit ? addition of caution to 11.4.2 operation of low-voltage detection (lvi) circuit ? modification of figure 11-9 lvi circuit operation timing chapter 11 power-on- clear circuits ? addition of 12.3 (2) port mode register 2 (pm2) chapter 12 bit sequential buffer ? addition of description of power supply voltage and osts oscillation stabilization time to table 17-1 differences between pd78e9860a, 78e9861a and mask rom versions chapter 17 pd78e9860a, 78e9861a chapter 20 electrical specifications chapter 21 example of rc oscillation frequency characteristics (reference values) chapter 22 package drawing chapter 23 recommended soldering conditions 4th addition of chapter appendix b notes on target system design

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